Improving the compensated Horner scheme with a Fused Multiply and Add

Proceedings of the ACM Symposium on Applied Computing

Volumn 2, Issue , 2006, Pages 1323-1327

  Graillat, Stef ^a   Langlois, Philippe ^a   Louvet, Nicolas ^a  

^a UNIVERSITÉ DE PERPIGNAN   (France)

Author keywords

Error free transformations; Fused Multiply and Add; Horner scheme; IEEE 754 floating point arithmetic; Polynomial evaluation

Indexed keywords

ALGORITHMS; MICROPROCESSOR CHIPS; OPTIMIZATION; POLYNOMIALS;

ERROR-FREE TRANSFORMATIONS; FUSED MULTIPLY AND ADD; HORNER SCHEME; IEEE-754 FLOATING POINT ARITHMETIC; POLYNOMIAL EVALUATION;

COMPUTER SOFTWARE;

EID: 33751031356     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1141277.1141585     Document Type: Conference Paper

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