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Volumn 2006, Issue , 2006, Pages 62-67

Application driven traffic modeling for NoCs

Author keywords

Applications; Networks on chip; QoS; Traffic modeling

Indexed keywords

ENERGY UTILIZATION; LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION; QUALITY OF SERVICE; SIGNAL INTERFERENCE; VIDEO SIGNAL PROCESSING;

EID: 33750897517     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1150343.1150364     Document Type: Conference Paper
Times cited : (27)

References (16)
  • 1
    • 0034428118 scopus 로고    scopus 로고
    • System-level design: Orthogonalization of concerns and platform-based design
    • Keutzer, K. et al. "System-Level Design: Orthogonalization of Concerns and Platform-Based Design". IEEE Transactions on Computer-Aided Design, v.19(12), 2000, pp. 1523-1543.
    • (2000) IEEE Transactions on Computer-aided Design , vol.19 , Issue.12 , pp. 1523-1543
    • Keutzer, K.1
  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Benini, L. De Micheli,G. "Networks on chips: a new SoC paradigm". IEEE Comp., v.35(1), 2002, pp. 70-78.
    • (2002) IEEE Comp. , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 3
    • 1242309790 scopus 로고    scopus 로고
    • QNoC: QoS architecture and design process for network on chip
    • Bolotin E. et al. "QNoC: QoS architecture and design process for network on chip". JSA, v.50(2-3), 2004, pp. 105-128.
    • (2004) JSA , vol.50 , Issue.2-3 , pp. 105-128
    • Bolotin, E.1
  • 4
    • 33646925675 scopus 로고    scopus 로고
    • A complete network-on-chip emulation framework
    • Genko, N. et al. "A Complete Network-On-Chip Emulation Framework". In: DATE'05, pp. 246-251.
    • DATE'05 , pp. 246-251
    • Genko, N.1
  • 5
    • 84861435320 scopus 로고    scopus 로고
    • MAIA - A framework for networks on chip generation and verification
    • Ost, L. et al. "MAIA - A Framework for Networks on Chip Generation and Verification". In: ASP-DAC'05, pp. 49-52.
    • ASP-DAC'05 , pp. 49-52
    • Ost, L.1
  • 6
    • 4444324957 scopus 로고    scopus 로고
    • Dyad - Smart routing for networks on chip
    • Hu, J.; Marculescu, R. "Dyad - Smart routing for networks on chip". In: DAC'04, pp. 260-263.
    • DAC'04 , pp. 260-263
    • Hu, J.1    Marculescu, R.2
  • 7
    • 0033307069 scopus 로고    scopus 로고
    • Investigating QoS support for traffic mixes with the media worm router
    • Yum, K. et al. "Investigating QoS Support for Traffic Mixes with the Media Worm Router". In: 6th HPCA'00, pp. 97-106.
    • 6th HPCA'00 , pp. 97-106
    • Yum, K.1
  • 8
    • 37849021721 scopus 로고    scopus 로고
    • On the impact of traffic statistics on quality of service for networks on chip
    • Santi, S. et al. "On the Impact of Traffic Statistics on Quality of Service for Networks on Chip". In: ISCAS'05, pp. 2349-2352.
    • ISCAS'05 , pp. 2349-2352
    • Santi, S.1
  • 9
    • 33750906036 scopus 로고    scopus 로고
    • Quantitative modelling an comparison of communication schemes to guarantee quality-of-service in networks-on-chip
    • Harmanci, M. et al. "Quantitative Modelling an Comparison of Communication Schemes to Guarantee Quality-of-Service in Networks-on-Chip". In: ISCAS'05, pp. 1782-1785.
    • ISCAS'05 , pp. 1782-1785
    • Harmanci, M.1
  • 12
    • 1342329326 scopus 로고    scopus 로고
    • On-chip traffic modeling and synthesis for MPEG-2 video applications
    • Varatkar, G.; Marculescu, R. "On-Chip Traffic Modeling and Synthesis for MPEG-2 Video Applications". IEEE Transactions on VLSI Systems, v. 12(1), 2004, pp. 108-119.
    • (2004) IEEE Transactions on VLSI Systems , vol.12 , Issue.1 , pp. 108-119
    • Varatkar, G.1    Marculescu, R.2
  • 13
    • 34250789577 scopus 로고    scopus 로고
    • Traffic generation and performance evaluation for mesh-based NoCs
    • Tedesco, L. et al. "Traffic Generation and Performance Evaluation for Mesh-Based NoCs". In: SBCCI'05, pp. 184-189.
    • SBCCI'05 , pp. 184-189
    • Tedesco, L.1
  • 14
    • 24144461667 scopus 로고    scopus 로고
    • Performance evaluation and design trade-offs for network-on-chip interconnect architectures
    • Pande, P. et al. "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures". IEEE Transactions on Computers, v.54(8), 2005, pp. 1025-1040.
    • (2005) IEEE Transactions on Computers , vol.54 , Issue.8 , pp. 1025-1040
    • Pande, P.1
  • 15
    • 0028377540 scopus 로고
    • On the self-similar nature of ethernet traffic
    • Leland, W. et al. "On the Self-Similar Nature of Ethernet Traffic". IEEE/ACM Transactions on Networking, v.2, 1994, pp. 1-15.
    • (1994) IEEE/ACM Transactions on Networking , vol.2 , pp. 1-15
    • Leland, W.1
  • 16
    • 9544237156 scopus 로고    scopus 로고
    • Hermes: An infrastructure for low area overhead packet-switching networks on chip
    • Moraes, F. et al. "Hermes: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip". Integration, the VLSI Journal, v.38(1), 2004, pp. 69-93.
    • (2004) Integration, the VLSI Journal , vol.38 , Issue.1 , pp. 69-93
    • Moraes, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.