Motion estimation operation implemented in FPGA chips for real-time image compression

International Symposium on Image and Signal Processing and Analysis, ISPA

Volumn 2001-January, Issue , 2001, Pages 399-404

  Ryszko, Andrzej ^a   Wiatr, Kazimierz ^a  

^a AGH UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33750707999     PISSN: 18455921     EISSN: 18492266     Source Type: Conference Proceeding    
DOI: 10.1109/ISPA.2001.938663     Document Type: Conference Paper

References (13)

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11. Wiatr K.: Dedicated System Architecture for a Real-Time Video Data Pre-Processing used Specialised Hardware Processors Implemented in FPGA Structures, Proc. of the IEEE International Workshop on Intelligent Signal Processing, Budapest 1999, pp. 294-299
12. Wiatr K., Russek P.: Embedded Zero Wavelet Coefficient Coding Method for FPGA Implementation of Video Codec in Real-Time Systems, Proc. of the IEEE International Conference on Information Technology: Coding and Computing ITCC'2000, Nevada 2000, IEEE Computer Society - Washington - Brussels - Tokyo 2000, pp. 146-151
13. Xilinx Inc.: The programmable logic data book. 2000