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Volumn 5, Issue , 1992, Pages 2152-2155

Numerical optimization-based synthesis of pipelined A/D converters

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINED OPTIMIZATION; OPERATIONAL AMPLIFIERS; PIPELINES;

EID: 33750501904     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.1992.230566     Document Type: Conference Paper
Times cited : (2)

References (10)
  • 1
    • 0026141224 scopus 로고
    • A 13-b 2.5-mhz self-calibrated pipelined a/d converter in 3-um CMOS
    • Dec.
    • Y.-M. Lin, B. Kim, and P. R. Gray. A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-um CMOS. IEEE J. Solid-State Circuits, 26(4):628-636, Dec. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.4 , pp. 628-636
    • Lin, Y.-M.1    Kim, B.2    Gray, P.R.3
  • 3
    • 0024908745 scopus 로고
    • OASYS: A framework for analog circuit synthesis
    • Dec.
    • R. Harjani, R. A. Rutenbar, and L. R. Carley. OASYS: A framework for analog circuit synthesis. IEEE Trans, on CAD, 8(12):1247-1266, Dec. 1989.
    • (1989) IEEE Trans, on CAD , vol.8 , Issue.12 , pp. 1247-1266
    • Harjani, R.1    Rutenbar, R.A.2    Carley, L.R.3
  • 4
    • 0027099476 scopus 로고
    • Automating analog circuit design using constrained optimization techniques
    • IEEE
    • P. C. Maulik and L. R. Carley. Automating Analog Circuit Design using Constrained Optimization Techniques. Proc. of IEEE International Conference on CAD, pages 390-393. IEEE, 1991.
    • (1991) Proc. of IEEE International Conference on CAD , pp. 390-393
    • Maulik, P.C.1    Carley, L.R.2
  • 5
    • 0023401686 scopus 로고
    • BSIM: Berkeley shortxihannel ig- fet model for mos transistors
    • Aug
    • B. J. Sheu et al., BSIM: Berkeley shortxihannel IG- FET model for MOS transistors. IEEE J. of Solid-State Circuits, 22(4):558-566, Aug. 1987
    • (1987) IEEE J. of Solid-State Circuits , vol.22 , Issue.4 , pp. 558-566
    • Sheu, B.J.1
  • 7
    • 85067260333 scopus 로고
    • A current-based positive-feedback technique for efficient cascode bootstrapping
    • Apr.
    • K. Nakamura and L. R. Carley. A Current-Based Positive-Feedback Technique for Efficient Cascode Bootstrapping. IEEE J. of Solid-State Circuits, Apr. 1992.
    • (1992) IEEE J. of Solid-State Circuits
    • Nakamura, K.1    Carley, L.R.2
  • 10
    • 0025414182 scopus 로고
    • Asymptotic waveform evaluation for timing analysis
    • Apr.
    • L. T. Pillage and R. A. Rohrer. Asymptotic waveform evaluation for timing analysis. IEEE Trans, on CAD, 9(4):352-366, Apr. 1990.
    • (1990) IEEE Trans, on CAD , vol.9 , Issue.4 , pp. 352-366
    • Pillage, L.T.1    Rohrer, R.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.