FPGA implementation of real-time image convolutions with three level of memory hierarchy

Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003

Volumn , Issue , 2003, Pages 424-427

  Jiang, Hongtu ^a   Öwall, Viktor ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; CONVOLUTION; DATA TRANSFER; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS;

BANDWIDTH REDUCTIONS; DATA-FLOW ARCHITECTURES; DEDICATED CONTROLLERS; FPGA IMPLEMENTATIONS; IMAGE CONVOLUTION; MEMORY HIERARCHY; OPTIMIZATION ARCHITECTURE; REAL TIME IMAGES;

MEMORY ARCHITECTURE;

EID: 33750216214     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2003.1275793     Document Type: Conference Paper

References (8)

1. F. K. Karadayi et al., Imaging with Texas Instruments' TMS320C64x, Texas Instruments White paper, Dec. 2001
2. E. Jamro et al., Convolution operation implemented in FPGA.structures for real-time image processing, Proceedings of the 2001 ISPA.
3. E. Jamro et al., FPGA implementation of addition as a part of the convolution, Proceedings of Euromicro Symposium on Digital Systems, Design, 2001
4. D. C. M. Bilsby et al, Comparison of a programmable DSP and a FPGA for real-time multiscale convolution, IEE Colloquium on High Performance Architectures for Real-Time Image Processing, 1998
5. V. Öwall, et al., "A Custom Image Convolution DSP with a Sustained Calculation Capacity of > 1 GMAC/s and Low I/O Bandwidth", The J, of VLSI Signal Processing, 335-350; Nov. 1999.
6. F. Catthoor et al., Custom memory management methodology, Kluwer acdemic Publishers, 1998
7. R. Rudell, "ESPRESSO - Boolean minimization program", Technical report, University of California at Berkeley, Dec. 1985.
8. V. Öwall, Synthesis of Controllers from a Range of Controller Architectures, Ph. D. Thesis, Lund University, Dec. 1994