-
1
-
-
0031364294
-
"A Survey of Techniques for Formal Verification of Combinational Circuit"
-
J. Jain, A. Narayan, M. Fujita, and A. Sangiovanni-Vincentelli, "A Survey of Techniques for Formal Verification of Combinational Circuit," Proc. Int'l Conf. Computer Design (ICCD), pp. 445-454, 1997.
-
(1997)
Proc. Int'l Conf. Computer Design (ICCD)
, pp. 445-454
-
-
Jain, J.1
Narayan, A.2
Fujita, M.3
Sangiovanni-Vincentelli, A.4
-
2
-
-
0017472779
-
"Proving the Correctness of Multiprocess Programs"
-
Mar
-
L. Lamport, "Proving the Correctness of Multiprocess Programs," IEEE Trans. Software Eng., vol. 3, no. 2, pp. 124-142, Mar. 1977.
-
(1977)
IEEE Trans. Software Eng.
, vol.3
, Issue.2
, pp. 124-142
-
-
Lamport, L.1
-
3
-
-
0005440654
-
"Formal Verification in Hardware Design: A Survey"
-
Apr
-
C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Trans. Design Automation of Electronic Systems, vol. 4, no. 2, pp. 123-193, Apr. 1999.
-
(1999)
ACM Trans. Design Automation of Electronic Systems
, vol.4
, Issue.2
, pp. 123-193
-
-
Kern, C.1
Greenstreet, M.2
-
4
-
-
33750128030
-
"Murø Description Language and Verifier"
-
"Murø Description Language and Verifier," http://sprout.stanford.edu/dill/murphi.html, 2006.
-
(2006)
-
-
-
6
-
-
33750140844
-
"The SMV System"
-
"The SMV System," http://www-2.cs.cmu.edu/~modelcheck/smv.html, 2006.
-
(2006)
-
-
-
8
-
-
84957068589
-
"Model Checking Based on Sequential ATPG"
-
V. Boppana, S.P. Rajan, K. Takayama, and M. Fujita, "Model Checking Based on Sequential ATPG" Proc. Computer-Aided Verification Conf. (CAV), pp. 418-430, 1999.
-
(1999)
Proc. Computer-Aided Verification Conf. (CAV)
, pp. 418-430
-
-
Boppana, V.1
Rajan, S.P.2
Takayama, K.3
Fujita, M.4
-
9
-
-
0033714214
-
"Assertion Checking by Combined Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques"
-
June
-
C.-Y. Huang and K.-T. Cheng, "Assertion Checking by Combined Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques," Proc. Design Automation Conf., pp. 118-123, June 2000.
-
(2000)
Proc. Design Automation Conf.
, pp. 118-123
-
-
Huang, C.-Y.1
Cheng, K.-T.2
-
10
-
-
0032630766
-
"Enhancing Simulation with BDDs and ATPG"
-
M.K. Ganai, A. Aziz, and A. Kuehlmann, "Enhancing Simulation with BDDs and ATPG," Proc. Design Automation Conf. (DAC), pp. 385-390, 1999.
-
(1999)
Proc. Design Automation Conf. (DAC)
, pp. 385-390
-
-
Ganai, M.K.1
Aziz, A.2
Kuehlmann, A.3
-
11
-
-
0346868422
-
"An Analysis of ATPG and SAT Algorithms for Formal Verification"
-
Nov
-
G. Parthasarathy, C.-Y. Huang, and K.-T. Cheng, "An Analysis of ATPG and SAT Algorithms for Formal Verification," Proc. High-Level Design Validation and Test Workshop, pp. 177-182, Nov. 2001.
-
(2001)
Proc. High-Level Design Validation and Test Workshop
, pp. 177-182
-
-
Parthasarathy, G.1
Huang, C.-Y.2
Cheng, K.-T.3
-
12
-
-
0036444496
-
"Verifying Properties Using Sequential ATPG"
-
J.A. Abraham, V.M. Vedula, and D.G. Saab, "Verifying Properties Using Sequential ATPG," Proc. Int'l Test Conf., pp. 194-202, 2002.
-
(2002)
Proc. Int'l Test Conf.
, pp. 194-202
-
-
Abraham, J.A.1
Vedula, V.M.2
Saab, D.G.3
-
13
-
-
2342667434
-
"Practical Use of Sequential ATPG for Model Checking: Going the Extra Mile Does Pay Off"
-
Nov
-
M. Hsiao and J. Jain, "Practical Use of Sequential ATPG for Model Checking: Going the Extra Mile Does Pay Off," Proc. High-Level Design Validation and Test Workshop, pp. 39-44, Nov. 2001.
-
(2001)
Proc. High-Level Design Validation and Test Workshop
, pp. 39-44
-
-
Hsiao, M.1
Jain, J.2
-
14
-
-
0036048611
-
"Effective Safety Property Checking Using Simulation-Based Sequential ATPG"
-
S. Sheng, K. Takayama, and M.S. Hsiao, "Effective Safety Property Checking Using Simulation-Based Sequential ATPG," Proc. Design Automation Conf. (DAC), pp. 813-818, 2002.
-
(2002)
Proc. Design Automation Conf. (DAC)
, pp. 813-818
-
-
Sheng, S.1
Takayama, K.2
Hsiao, M.S.3
-
15
-
-
0032630134
-
"Symbolic Model Checking Using SAT Procedures instead of BDDs"
-
A. Biere, A. Cimatti, E.M. Clarke, M. Fujita, and Y. Zhu, "Symbolic Model Checking Using SAT Procedures instead of BDDs," Proc. Design Automation Conf., pp. 317-320, 1999.
-
(1999)
Proc. Design Automation Conf.
, pp. 317-320
-
-
Biere, A.1
Cimatti, A.2
Clarke, E.M.3
Fujita, M.4
Zhu, Y.5
-
16
-
-
0032680865
-
"GRASP: A Search Algorithm for Propositional Satisfiability"
-
May
-
J.P. Marques-Silva and K.A. Sakallah, "GRASP: A Search Algorithm for Propositional Satisfiability," IEEE Trans. Computers, vol. 48, no. 5, pp. 506-521, May 1999.
-
(1999)
IEEE Trans. Computers
, vol.48
, Issue.5
, pp. 506-521
-
-
Marques-Silva, J.P.1
Sakallah, K.A.2
-
17
-
-
0034852165
-
"Chaff: Engineering an Efficient SAT Solver"
-
M.W. Moskewicz, C.F. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT Solver," Proc. Design Automation Conf., pp. 530-535, 2001.
-
(2001)
Proc. Design Automation Conf.
, pp. 530-535
-
-
Moskewicz, M.W.1
Madigan, C.F.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
18
-
-
0142184816
-
"Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal"
-
Q. Wu and M.S. Hsiao, "Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal," Proc. Int'l Test Conf., pp. 281-289, 2003.
-
(2003)
Proc. Int'l Test Conf.
, pp. 281-289
-
-
Wu, Q.1
Hsiao, M.S.2
-
19
-
-
3142683888
-
"Efficient ATPG for Design Validation Based on Partitioned State Exploration Histories"
-
Q. Wu and M.S. Hsiao, "Efficient ATPG for Design Validation Based on Partitioned State Exploration Histories," Proc. VLSI Test Symp., pp. 389-394, 2004.
-
(2004)
Proc. VLSI Test Symp.
, pp. 389-394
-
-
Wu, Q.1
Hsiao, M.S.2
-
20
-
-
18144367017
-
"State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation"
-
Q. Wu and M.S. Hsiao, "State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation," Proc. Int'l Test Conf., pp. 820-829, 2004.
-
(2004)
Proc. Int'l Test Conf.
, pp. 820-829
-
-
Wu, Q.1
Hsiao, M.S.2
-
22
-
-
0022706656
-
"Automatic Verification of Finite State Concurrent Systems Using Temporal Logic Specifications"
-
E. Clarke, E.A. Emerson, and A. Sistla, "Automatic Verification of Finite State Concurrent Systems Using Temporal Logic Specifications," ACM Trans. Programming Languages and Systems, vol. 1, no. 2, pp. 244-263, 1986.
-
(1986)
ACM Trans. Programming Languages and Systems
, vol.1
, Issue.2
, pp. 244-263
-
-
Clarke, E.1
Emerson, E.A.2
Sistla, A.3
-
24
-
-
0003872611
-
"Improvements to Propositional Satisfiability Search Algorithms"
-
PhD dissertation, Dept. of Computer and Information Science, Univ. of Pennsylvania, May
-
J.W. Freeman, "Improvements to Propositional Satisfiability Search Algorithms," PhD dissertation, Dept. of Computer and Information Science, Univ. of Pennsylvania, May 1995.
-
(1995)
-
-
Freeman, J.W.1
-
25
-
-
84893675417
-
"A Rearrangement Search Strategy for Determining Propositional Satisfiability"
-
R. Zabih and D.A. McAllester, "A Rearrangement Search Strategy for Determining Propositional Satisfiability," Proc. Nat'l Conf. Artificial Intelligence, pp. 155-160, 1988.
-
(1988)
Proc. Nat'l Conf. Artificial Intelligence
, pp. 155-160
-
-
Zabih, R.1
McAllester, D.A.2
-
26
-
-
84881072062
-
"A Computing Procedure for Quantification Theory"
-
M. Davis and H. Putnam, "A Computing Procedure for Quantification Theory," J. ACM, vol. 7, pp. 201-215, 1960.
-
(1960)
J. ACM
, vol.7
, pp. 201-215
-
-
Davis, M.1
Putnam, H.2
-
27
-
-
33750133353
-
"Genetic Algorithm Tutorial Home Page"
-
"Genetic Algorithm Tutorial Home Page," http://www.estec.esa.nl/outreach/gatutor/Default.htm, 2005.
-
(2005)
-
-
-
29
-
-
0030686639
-
"Static Logic Implication with Application to Fast Redundancy Identification"
-
J.-K. Zhao, E.M. Rudnick, and J.H. Patel, "Static Logic Implication with Application to Fast Redundancy Identification," Proc. VLSI Test Symp., pp. 288-293, 1997.
-
(1997)
Proc. VLSI Test Symp.
, pp. 288-293
-
-
Zhao, J.-K.1
Rudnick, E.M.2
Patel, J.H.3
-
30
-
-
0024913805
-
"Combinational Profiles of Sequential Benchmark Circuits"
-
F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. Int'l Symp. Circuits and Systems, pp. 1929-1934, 1989.
-
(1989)
Proc. Int'l Symp. Circuits and Systems
, pp. 1929-1934
-
-
Brglez, F.1
Bryan, D.2
Kozminski, K.3
-
31
-
-
0027072656
-
"HITEC: A Test Generation Package for Sequential Circuits"
-
S. Davidson, M. Niermann, and J.H. Patel, "HITEC: A Test Generation Package for Sequential Circuits," Proc. European Design Automation Conf., pp. 214-218, 1991.
-
(1991)
Proc. European Design Automation Conf.
, pp. 214-218
-
-
Davidson, S.1
Niermann, M.2
Patel, J.H.3
-
32
-
-
0030652729
-
"Sequential Circuit Test Generation Using Dynamic State Traversal"
-
M.S. Hsiao, E.M. Rudnick, and J.H. Patel, "Sequential Circuit Test Generation Using Dynamic State Traversal," Proc. European Design and Test Conf., pp. 22-28, 1997.
-
(1997)
Proc. European Design and Test Conf.
, pp. 22-28
-
-
Hsiao, M.S.1
Rudnick, E.M.2
Patel, J.H.3
|