Learning for evolutionary design

Proceedings - NASA/DoD Conference on Evolvable Hardware, EH

Volumn 2003-January, Issue , 2003, Pages 17-20

  Louis, S J ^a  

^a University of Nevada   (United States)

Author keywords

Adders; Algorithm design and analysis; Circuit testing; Computer science; Genetic algorithms; Hardware; Laboratories; Logic circuits; Logic design; Logic testing

Indexed keywords

ADDERS; ALGORITHMS; COMPUTER HARDWARE; COMPUTER SCIENCE; COMPUTER TESTING; DESIGN; ELECTRIC NETWORK ANALYSIS; GENETIC ALGORITHMS; HARDWARE; LABORATORIES; LOGIC DESIGN; NASA;

ALGORITHM DESIGN AND ANALYSIS; CIRCUIT TESTING; COMBINATION LOGIC; COMBINATIONAL LOGIC; CONFIGURATION DESIGNS; EVOLUTIONARY DESIGN; LOGIC TESTING; SIMILAR SOLUTION;

LOGIC CIRCUITS;

EID: 33750047605     PISSN: 15506029     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EH.2003.1217637     Document Type: Conference Paper

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