Clock jitter in direct RF and if sampling wireless receivers

IEE Proceedings: Circuits, Devices and Systems

Volumn 153, Issue 4, 2006, Pages 346-350

  Chalvatzis, T ^a   Gagnon, E ^b   Wight, J S ^c  

^a UNIVERSITY OF TORONTO   (Canada)

^b NORTEL NETWORKS   (Canada)

^c CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCKING SIGNALS; POWER SPECTRAL DENSITY (PSD); SIGNAL FREQUENCY;

ANALOG TO DIGITAL CONVERSION; CLOCKS; COMPUTER SIMULATION; NATURAL FREQUENCIES; SIGNAL RECEIVERS; SIGNAL TO NOISE RATIO; WIRELESS TELECOMMUNICATION SYSTEMS;

TIMING JITTER;

EID: 33749827839     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20050154     Document Type: Conference Paper

References (8)

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3. Brannon, B.: 'Aperture uncertainty and ADC system performance', Analog Devices Application Note, AN-501, 1998
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5. Da Dalt, N., Harteneck, M., Sandner, C., and Wiesbauer, A.: ' On the jitter requirements of the sampling clock for analog-to-digital converters ', IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 2002, 49, (9), p. 1354-1360 10.1109/TCSI.2002.802353 1057-7122
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7. ANSI/TIA/EIA-97-D-2001
8. Chalvatzis, T.: ' Superconductive analog-to-digital converters in wireless radio applications ', 2003, MASc, Carleton University, Canada