Methods for partitioning the system and performance evaluation in power-hardware-in-the-loop simulations - Part I

IECON Proceedings (Industrial Electronics Conference)

Volumn 2005, Issue , 2005, Pages 251-256

  Wu, Xin ^a   Monti, Antonello ^b  

^a ANSOFT CORPORATION   (United States)

^b University of South Carolina   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIRST ORDER SYSTEMS; HARDWARE INTERFACES; PERFORMANCE EVALUATIONS; POWERHARDWARE IN THE LOOP (PHIL) SIMULATIONS;

APPROXIMATION THEORY; COMPUTER SIMULATION; COMPUTER SYSTEMS; COMPUTER TESTING; INTERFACES (COMPUTER);

COMPUTER HARDWARE;

EID: 33749659914     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IECON.2005.1568912     Document Type: Conference Paper

References (5)

1. S. Ayasun, A. Monti, R. Dougal, S. Vallieu, and R. Fischl. "On the Stability of Hardware in the Loop Simulation", ELECTRIMACS 2002, August 2002, Montreal, Canada.
2. IEEE P1076 VHDL Standard. Available at: http://standards.ieee.org/.
3. M. Vetterli, J. Kovacevic. Wavelets and subband coding. Prentice Hall PTR, NJ, 1995.
4. S. Ayasun, S. Vallieu, R. Fischl, and T. Chmielewski. "Electric Machinery Diagnostic/Testing System and Power Hardware-In-the-Loop Studies", Symposium on Diagnostics for Electric Machines, Power Electronics and Drives. Aug. 2003, Atlanta, GA.
5. S.Y.R. Hui and C. Christopoulos. "Numerical modeling of power circuits using transmission-line modeling". Proc. IEEE on Power Electronics. Vol. 6, No. 3, Oct. 1991, PP636-644.