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Volumn 4137 LNCS, Issue , 2006, Pages 465-476

On interleaving in timed automata

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTABILITY AND DECIDABILITY; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; DATA ACQUISITION; PROBLEM SOLVING; THEOREM PROVING;

EID: 33749577849     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11817949_31     Document Type: Conference Paper
Times cited : (34)

References (19)
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  • 3
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    • On timing analysis of combinational circuits
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    • Ben Salah, R.1    Bozga, M.2    Maler, O.3
  • 5
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    • IF-2.0: A validation environment for component-based real-time systems
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    • (2002) CAV'02 , pp. 343-348
    • Bozga, M.1    Graf, S.2    Mounier, L.3
  • 6
    • 2542637110 scopus 로고    scopus 로고
    • Partial-order reduction techniques for real-time model checking
    • [DGKK98]
    • [DGKK98] D. Dams, R. Gerth, B. Knaack and R. Kuiper, Partial-order Reduction Techniques for Real-time Model Checking, Formal Aspects of Computing 10, 469-482, 1998.
    • (1998) Formal Aspects of Computing , vol.10 , pp. 469-482
    • Dams, D.1    Gerth, R.2    Knaack, B.3    Kuiper, R.4
  • 7
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    • Model checking of real-time reachability properties using abstractions
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    • [DT98] C. Daws and S. Tripakis, Model Checking of Real-Time Reachability Properties Using Abstractions, TACAS'98, 313-329, 1998.
    • (1998) TACAS'98 , pp. 313-329
    • Daws, C.1    Tripakis, S.2
  • 8
    • 0030414046 scopus 로고    scopus 로고
    • Reducing the number of clock variables of timed automata
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    • [DY96] C. Daws and S. Yovine, Reducing the Number of Clock Variables of Timed Automata, RTSS '96, 73-81, 1996.
    • (1996) RTSS '96 , pp. 73-81
    • Daws, C.1    Yovine, S.2
  • 9
    • 0004024352 scopus 로고
    • [DR95] V. Diekert and G. Rozenberg (Eds.), World Scientific
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    • (1995) The Book of Traces
  • 12
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    • A partial order semantics approach to the clock explosion problem of timed automata
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    • [LNZ05] D. Lugiez, P. Niebert and S. Zennou, A Partial Order Semantics Approach to the Clock Explosion Problem of Timed Automata, Theoretical Computer Science 345, 27-59, 2005.
    • (2005) Theoretical Computer Science , vol.345 , pp. 27-59
    • Lugiez, D.1    Niebert, P.2    Zennou, S.3
  • 13
    • 84948173788 scopus 로고
    • Timing analysis of asynchronous circuits using timed automata
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    • [MP95] O. Maler and A. Pnueli, Timing Analysis of Asynchronous Circuits using Timed Automata, CHARME'95, 189-205, 1995.
    • (1995) CHARME'95 , pp. 189-205
    • Maler, O.1    Pnueli, A.2
  • 14
    • 84888251041 scopus 로고    scopus 로고
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  • 19
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    • ELSE: A new symbolic state generator for timed automata
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    • [ZYN03] S. Zennou, M. Yguel and P. Niebert, ELSE: A New Symbolic State Generator for Timed Automata, FORMATS'03, 273-280, 2003.
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    • Zennou, S.1    Yguel, M.2    Niebert, P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.