Applying a counter-based PWM control scheme to an FPGA-based SR forward converter

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn 2006, Issue , 2006, Pages 1396-1400

  Hwu, K I ^a   Yau, Y T ^b  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

FEEDBACK OUTPUT VOLTAGE; SYNCHRONOUS RECTIFICATION (SR); SYSTEM ON PROGRAMMABLE CHIP (SOPC);

ANALOG TO DIGITAL CONVERSION; COMPARATOR CIRCUITS; ELECTRIC CONTROL EQUIPMENT; ELECTRIC RECTIFIERS; FIELD PROGRAMMABLE GATE ARRAYS; PULSE WIDTH MODULATION; THREE TERM CONTROL SYSTEMS;

POWER CONVERTERS;

EID: 33749517378     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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4. Guo Liping, J. Y. Hung and R. M. Nelms, "PID controller modifications to improve steady-state performance of digital controllers for buck and boost converters," IEEE APEC'02, vol.1, pp. 381-388, 2002.
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6. A. P. Dancy and A. P. Chandrakaasan, "Ultra low power circuits for PWM converters," IEEE PESC'97,vol. 1, pp. 21-27, 1997.