Physics of deep submicron CMOS VLSI

AIP Conference Proceedings

Volumn 772, Issue , 2005, Pages 1591-1594

  Buss, Dennis D ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33749481907     PISSN: 0094243X     EISSN: 15517616     Source Type: Conference Proceeding    
DOI: 10.1063/1.1994727     Document Type: Conference Paper

References (10)

1. Semiconductor Electronics Education Committee (SEEC) Books, Seven volumes published in 1964 by John Wiley & Sons Inc.
2. For example, Ben Streetman and Sanjay Bannerjee, Solid State Electronic Devices. Prentice Hall, 2000.
3. 2003 International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2003.
4. R. Denard et al. "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions", IEEE J. SolidState Circuits, SC-9, pp 256-268.
5. Luigi Colombo. Private communication
6. F. Stern, "Quantum and Continuum Results for Inversion Layers", Proc of the Tenth International Conf on the Physics of Semiconductors, Aug 1970, pp 451458.
7. S. Takagi, J.L. Hoyt, J. Welser, and J.F. Gibbons, "Comparative study of phonon-limited mobility of twodimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors," J. Appl. Phys. 80, pp. 1567-1577, August 1996
8. M. V. Fischetti et al, "Six-band kP calculation of the hole mobility in silicon inversion layers: Dependence of surface orientation, strain and silicon thickness", Jol of Applied Physics, 94, 15 July 2003, pp 1079-1095
9. M. Giles et al, "Understanding Stress Enhanced Performance in Intel 90 nm CMOS Technology", 2004 Symposium on VLSI Technology Digest of Technical Papers, pp 118-119.
10. P. R. Chidambaram et al, "35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS" 2004 Symposium on VLSI Technology Digest of Technical Papers, June 2004, to pp 48-49.