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Volumn , Issue , 2005, Pages 4835-4838

An Nth order central symmetrical layout pattern for nonlinear gradients cancellation

Author keywords

[No Author keywords available]

Indexed keywords

FLEXIBLE CELL; GRADIENT EFFECT; LAYOUT PATTERNS; SIMULATION RESULT; UNIT CELLS;

EID: 33749343225     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465715     Document Type: Conference Paper
Times cited : (17)

References (8)
  • 1
    • 0037346346 scopus 로고    scopus 로고
    • Understanding MOSFET mismatch for analog design
    • Mar
    • P. Drennan, C. McAndrew, "Understanding MOSFET mismatch for analog design," IEEE J. Solid-State Circuits, vol. 38, issue. 3, pp. 450-456, Mar. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.3 , pp. 450-456
    • Drennan, P.1    McAndrew, C.2
  • 2
    • 0025384744 scopus 로고
    • A voltage-controllable linear MOS transconductor using bias offset technique
    • Feb
    • Z. Wang, W. Guggenbuhl, "A voltage-controllable linear MOS transconductor using bias offset technique," IEEE J. Solid-State Circuits, vol. 25, issue. 1, pp. 315-317, Feb. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , Issue.1 , pp. 315-317
    • Wang, Z.1    Guggenbuhl, W.2
  • 5
    • 0022891057 scopus 로고
    • Characterization and modeling of mismatch in MOS transistors for precision analog design
    • K. Lakshmikumar, R. Hadaway, and M. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, 1986.
    • (1986) IEEE J. Solid-State Circuits , vol.SC-21 , pp. 1057-1066
    • Lakshmikumar, K.1    Hadaway, R.2    Copeland, M.3
  • 6
    • 4344569718 scopus 로고    scopus 로고
    • th order circular symmetry pattern and hexagonal tesselation: two new layout techniques cancelling nonlinear gradient, Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on , 1, pp. 237-240, May 2004.
    • th order circular symmetry pattern and hexagonal tesselation: two new layout techniques cancelling nonlinear gradient," Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on , vol. 1, pp. 237-240, May 2004.
  • 7
    • 0028714919 scopus 로고
    • Measurement and Modeling of MOS Transistor Current Mismatch in Analog IC's
    • Eric Felt, "Measurement and Modeling of MOS Transistor Current Mismatch in Analog IC's," Proc. of ACM, pp. 272-277, 1994.
    • (1994) Proc. of ACM , pp. 272-277
    • Felt, E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.