A flexible architecture for block turbo decoders using BCH or reed-solomon components codes

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

Volumn 2006, Issue , 2006, Pages 430-431

  Piriou, Erwan ^a   Jego, Christophe ^a   Adde, Patrick ^a   Jezequel, Michel ^a  

^a ECOLE DES MINES DE NANTES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY CODES; BLOCK CODES; COMPUTER ARCHITECTURE; POWER ELECTRONICS; REED RELAYS; TURBO CODES;

BLOCK TURBO DECODERS; DOUBLE CORRECTION POWER; REED SOLOMON CODES; SISO DECODERS;

DECODING;

EID: 33749343021     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2006.2     Document Type: Conference Paper

References (4)

1. C. Berrou, A. Glavieux, P. Thitimajshima, Near Shannon limit error correcting coding and decoding: Turbo Codes, IEEE ICC93, vol. 2/3, May 1993.
2. R. Pyndiah, A. Glavieux, A. Picart, S. Jacq, Near optimum decoding of product codes, GLOBECOM94, November 1994.
3. R. Pyndiah, P. Adde, R. Zhou, Block Turbo Codes: Ten years later, IEE Seminar on Sparse Graph Codes, October 2004.
4. R. Zhou, A. Picart, R. Pyndiah, A. Goalie, Reliable transmission low complexity Reed Solomon block turbo codes, ISWCS Conference, pp 193-197, September 2004.