A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 371-374

  Joshi, Rajiv V ^a   Chan, Yuen ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIER DIFFERENTIALS; DIFFERENTIAL (ANALOG) SIGNALS; DIFFERENTIAL CIRCUITS; PROGRAMMABLE VOLTAGE DIVIDER CIRCUITS;

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; COMPUTER HARDWARE; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; VOLTAGE DIVIDERS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 33749164917     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541637     Document Type: Conference Paper

References (3)

1. R. V. Joshi et. al., IEEE European Solid State Circuit Conf, Sept 2004, pp. 200-204.
2. R.V. Joshi, et al., IEEE Symposium on VLSI Circuits, 2002, pp 74-77.
3. R. D. Adams et al., IEEE International Test Conf., Aug. 1997, pp. 217-225.