The restrain of the dead time effects in parallel inverters

2005 IEEE International Conference on Electric Machines and Drives

Volumn , Issue , 2005, Pages 797-802

  Zhang, Yu ^a   Chen, Xikun ^a   Kang, Yong ^a   Chen, Jian ^a  

^a HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

Author keywords

Circulating currents; Dead time; Inverter; Parallel

Indexed keywords

DISTORTION (WAVES); ELECTRIC CURRENTS; ELECTRIC POTENTIAL; FEEDBACK CONTROL; VOLTAGE REGULATORS;

CIRCULATING CURRENTS; DEAD TIME; LOAD SHARE REGULATORS; PARALLEL INVERTERS;

ELECTRIC INVERTERS;

EID: 33749067200     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Jeong Seung-Gi, Lee Bang-Sup, Kim Kyung-Seo, Park Min-Ho. "The analysis and compensation of dead time effects in PWM Inverters". IEEE Trans. Industry Electronics, 1991, 38 (2): 108-114.
2. N. Mohan, M. T. Undeland, W. P. Robbins. "Power Electronics - Converters, Applications, and Design". Third Edition. John Wiley & Sons Inc. 2003.
3. B. K. Bose. "Modem Power Electronics and AC Drives", Prentice Hall., 2002.
4. M. Prodanovic, T. C. Green, H. Mansir. "A survey of control methods for three-phase inverters in parallel connection" Power Electronics and Variable Speed Drives, 2000. Eighth International Conference on (IEE Conf. Publ. No. 475), 2000: 472-477.
5. M. Ryan, "Control topology options for single phase UPS inverters", IEEE Trans. Industry Application. Vol. 33, No. 2, 1997, pp. 493-501.