-
2
-
-
33749060025
-
-
N. Giambiasi, A. Miara, Silog: a practical tool for digital logic circuit simulation, in: Proceedings of the Design Automation Conference D.A.C, San Diego, 1976.
-
-
-
-
3
-
-
33749048974
-
-
N. Giambiasi, A. Miara, D. Murach, Silog: a practical tool for logic digital network simulation, in: Proceedings of the Design Automation Conference D.A.C, San Diego, 1979.
-
-
-
-
4
-
-
33749060252
-
-
S. Ghosh, N. Giambiasi, On the need for consistency between the VHDL language constructs and the underlying hardware design, in: Proceedings of the European Simulation Symposium ESS 1996, Genoa, Italy.
-
-
-
-
5
-
-
0030386399
-
-
P. Walker, S. Ghosh, On the nature and inadequacies of transport timing delay constructs in VHDL, in: IEEE Conference on Computer Design, Austin, TX, 1996.
-
-
-
-
6
-
-
33749055994
-
-
M. Smaili, N. Giambiasi, C. Frydman, Discrete event simulation with fuzzy dates, in: Proceedings of the European Simulation Symposium ESS 1994 Istanbul, Turkey; M. Smaili, Modélisation à retards flous de circuits logiques en vue de leur simulation. Ph.D Université de Montpellier II, 1994.
-
-
-
-
7
-
-
33749078372
-
-
Introduction to VHDL, Mentor Graphics Corporation, 1993.
-
-
-
-
10
-
-
33749057761
-
-
TEGAS Reference Manual, G.E. CALMA, Milipitas, CA.
-
-
-
-
12
-
-
24344458811
-
Advances in asynchronous circuit theory. Part II: Bounded inertial delay model, MOS circuits, design techniques
-
Brzowzowski J.A., and Seger C.-H. Advances in asynchronous circuit theory. Part II: Bounded inertial delay model, MOS circuits, design techniques. EATCS Bulletin 43 (1991) 199-263
-
(1991)
EATCS Bulletin
, vol.43
, pp. 199-263
-
-
Brzowzowski, J.A.1
Seger, C.-H.2
-
13
-
-
33749081211
-
-
B. Magnhagen, Probability based verification of time margins in digital design, Ph.D Thesis, Linkoping, Sweden, 1977.
-
-
-
-
16
-
-
33749074337
-
-
M.C. Seong, T.G. Kim, Real time DEVS simulation: concurrent time-selective execution of combined RT-DEVS model and interactive environment, in: Proceedings of SCSC 1998, Reno, NV.
-
-
-
-
18
-
-
33749077588
-
-
J.L. Paillet, N. Giambiasi, Discrete event calculus models a high level specification for discrete event systems, in: Proceedings of the International Symposium ESS 1998, Nottingham, UK 1998, pp. 29-33.
-
-
-
-
19
-
-
1642436960
-
-
N. Giambiasi, J.L. Paillet, F. Châne, From timed automata to DEVS models, in: Proceedings of the Winter Simulation Conference WinterSim 2003, 2003, pp. 923-931.
-
-
-
-
20
-
-
33749054938
-
-
IEEE Standard VHDL Language Reference Manual, IEEE, 1988.
-
-
-
-
21
-
-
0024771474
-
A preemptive scheduling mechanism for accurate behavioral simulation of digital designs
-
Ghosh S., and Meng-Lin Yu. A preemptive scheduling mechanism for accurate behavioral simulation of digital designs. IEEE Transactions on Computers 38 11 (1989) 1595-1600
-
(1989)
IEEE Transactions on Computers
, vol.38
, Issue.11
, pp. 1595-1600
-
-
Ghosh, S.1
Meng-Lin, Yu.2
-
23
-
-
33749076501
-
-
H. Praehofer, System theoretic foundations for combined discrete-continuous system simulation. Ph.D, Kepler J. University of Linz, Austria, 1991. Also, H. Praehofer, System theoretic formalisms for combined discrete-continuous system simulation. International Journal of General Systems 19 (1991) 219-240.
-
-
-
|