A survey on system-on-a-chip design languages

Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Volumn , Issue , 2003, Pages 212-215

  Habibi, A ^a   Tahar, S ^a  

^a Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

Computational modeling; Conferences; Design automation; Hardware design languages; Information analysis; Java; Predictive models; Real time systems; System level design; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL LINGUISTICS; COMPUTER AIDED DESIGN; DESIGN; INFORMATION ANALYSIS; INTERACTIVE COMPUTER SYSTEMS; JAVA PROGRAMMING LANGUAGE; LARGE SCALE SYSTEMS; MICROELECTRONICS; MICROPROCESSOR CHIPS; MODELING LANGUAGES; PROGRAM PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS; REAL TIME SYSTEMS; SYSTEM-ON-CHIP;

COMPUTATIONAL MODEL; CONFERENCES; DESIGN AUTOMATIONS; HARDWARE DESIGN LANGUAGE; JAVA; PREDICTIVE MODELS; SYSTEM LEVEL DESIGN; SYSTEM ON A CHIP;

INTEGRATED CIRCUIT DESIGN;

EID: 33749035154     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2003.1213037     Document Type: Conference Paper

References (27)

1. P. Alexander and D. Barton, "A Tutorial Introduction to Rosetta," Hardware Description Languages Conference, San Jose, CA., March 2001.
2. P. Alexander, R. Kamath and D. Barton, "System Specification in Rosetta", presented at the IEEE Engineering of Computer Based Systems Symposium, Nashville, Edinburgh, UK. April 2000.
3. P. Bellows and B. Hutchings, "JHDL - An HDL for Reconfigurable Systems", IEEE Symposium on FPGAs for Custom Computing Machines",IEEE Computer Society Press",Los Alamitos, CA, Kenneth L. Pocek and Jeffrey Arnold, pp. 175-184, 1998.
4. Cadence Design Systems, 919 E. Hillsdale Blvd., Foster City, CA 94404, USA, SPW User's Manual.
5. CynApps, Inc. "Cynlib: A C++ Library for Hardware Description Reference Manual". Santa Clara, CA, USA, 1999.
6. G. De Micheli and D. C. Ku, HERCULES - A System for High-Level Synthesis, Proceedings of the 25th ACM/IEEE conference on Design automation, Atlantic City, New Jersey, United States, pp. 483-488, 1988.
7. G. De Micheli, "Hardware Synthesis from C/C++ models", Proceedings of the conference on Design, automation and test in Europe, Munich, Germany, pp. 80, 1999.
8. R. Domer, D. D. Gajski, A. Gerstlauer, S. Zhao and J. Zhu, "SpecC: Specification Language and Methodology", Kluwer Academic Publishers, 2000, pp 313.
9. B. P. Douglass, "Real-Time UML", Addison-Wesley, 2000.
10. P. L. Flake and Simon J. Davidmann, "SuperLog, a unified design language for system-on-chip", Proceedings of the Asia and South Pacific Design Automation Conference, pp. 583 -586, 2000.
11. R. Goering, "Mentor adds C interface to verification environment", EE Times, Feb. 2002.
12. B. Hutchings and B. Nelson, "Using General-Purpose Programming Languages for FPGA Design", Proceedings of Design Automation Conference, pp. 561-566, June 2000.
13. IEEE Std. 1364-2001, IEEE Standard for Verilog Hardware Description Language, 2001.
14. A. A. Jerraya et al., "Multilanguage Specification for System Design and Codesign", In System Level Synthesis, NATO ASI, 1998.
15. D. C. Ku, G. De Micheli, "High-level Synthesis and Optimization Strategies in Hercules/Hebe", Proceedings of the European Event in ASIC Design (EuroASIC) Conference, Paris, France, May 1990.
16. D.C. Ku and G. DeMicheli. "Hardware C - a language for hardware design", Technical Report CSL-TR-88-362, Computer Systems Lab, Stanford University, August 1988.
17. C. Maxfield, "A plethora of languages", EE Design, August 2001.
18. M. Meixner, J. Becker, Th. Hollstein, M. Glesner. "Object Oriented Specification Approach for Synthesis of Hardware-/Software Systems." Proc. GI/ITG/GMM Workshop Methoden und Beschreibungsprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 1999.
19. ModelSim, "Foreign Language Interface", User Manual, Version 5.5e, Aug 2001.
20. S. Ohr, "DSP design tools shift to SystemC", EE Times, Mar 2002.
21. R. Roth and D. Ramanathan. "A High-Level Hardware Design Methodology Using C++" 4th High Level Design Validation and Test Workshop, San Diego, pp 73-80, 1999.
22. J. Rumbaugh, I. Jacobson and G. Booch, "The Unified Modeling Language Reference Manual", Addison-Wesley, 1999.
23. M. Santarini, "System-level languages won't appear overnight, experts say", EE Times, March 2001.
24. SuperLog. http://www.SuperLog.org, 2003.
25. S. Sutherland, The Verilog PLI Handbook, Kluwer Academic Publishers, 1999.
26. S. Swan, "An Introduction to System Level Modeling in SystemC 2.0", Open SystemC Initiative Cadence Design Systems, Inc. May 2001.
27. SystemC. http://www.SystemC.org, 2003.