메뉴 건너뛰기




Volumn 5, Issue 5, 2006, Pages 446-453

Effect of conductance variability on resistor-logic demultiplexers for nanoelectronics

Author keywords

Demultiplexing; Error correction coding; Nanotechnology; Resistive circuits; Voltage dividers

Indexed keywords

ERROR CORRECTION CODING; MICROELECTRONIC CIRCUITRY; RESISTIVE CIRCUITS;

EID: 33748996756     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2006.880405     Document Type: Article
Times cited : (8)

References (19)
  • 2
    • 0141499770 scopus 로고    scopus 로고
    • Array-based architecture for FET-based, nanoscale electronics
    • Mar.
    • A. DeHon, "Array-based architecture for FET-based, nanoscale electronics," IEEE Trans. Nanotechnol., vol. 2, no. 1, pp. 23-32, Mar. 2003.
    • (2003) IEEE Trans. Nanotechnol. , vol.2 , Issue.1 , pp. 23-32
    • DeHon, A.1
  • 6
    • 16244364411 scopus 로고    scopus 로고
    • Nanoelectronic architectures
    • Mar.
    • G. Snider, P. J. Kuekes, and R. S. Williams, "Nanoelectronic architectures," Appl. Phys. A, vol. 80, pp. 1183-1196, Mar. 2005.
    • (2005) Appl. Phys. A , vol.80 , pp. 1183-1196
    • Snider, G.1    Kuekes, P.J.2    Williams, R.S.3
  • 7
    • 0344012623 scopus 로고    scopus 로고
    • Nanowire crossbar arrays as address decoders for integrated nanosystems
    • Z. Zhong, D. Wang, Y. Cui, M. W. Bockrath, and C. M. Lieber, "Nanowire crossbar arrays as address decoders for integrated nanosystems," Science, vol. 302, pp. 1377-1379, 2003.
    • (2003) Science , vol.302 , pp. 1377-1379
    • Zhong, Z.1    Wang, D.2    Cui, Y.3    Bockrath, M.W.4    Lieber, C.M.5
  • 9
    • 31944451658 scopus 로고    scopus 로고
    • Resistor-logic demultiplexers for nanoelectronics based on constant-weight codes
    • P. J. Kuekes, W. Robinett, R. M. Roth, G. Seroussi, G. S. Snider, and R. S. Williams, "Resistor-logic demultiplexers for nanoelectronics based on constant-weight codes," Nanotechnology, vol. 17, pp. 1052-1061, 2006.
    • (2006) Nanotechnology , vol.17 , pp. 1052-1061
    • Kuekes, P.J.1    Robinett, W.2    Roth, R.M.3    Seroussi, G.4    Snider, G.S.5    Williams, R.S.6
  • 10
    • 18744397824 scopus 로고    scopus 로고
    • Defect-tolerant interconnect to nanoelectronic circuits: Internally-redundant demultiplexers based on error-correcting codes
    • P. J. Kuekes, W. Robinett, G. Seroussi, and R. S. Williams, "Defect-tolerant interconnect to nanoelectronic circuits: internally-redundant demultiplexers based on error-correcting codes," Nanotechnology, vol. 16, pp. 869-882, 2005.
    • (2005) Nanotechnology , vol.16 , pp. 869-882
    • Kuekes, P.J.1    Robinett, W.2    Seroussi, G.3    Williams, R.S.4
  • 11
    • 23444432868 scopus 로고    scopus 로고
    • Improved voltage margins using linear error-correcting codes in resistor-logic demultiplexers for nanoelectronics
    • P. J. Kuekes, W. Robinett, and R. S. Williams, "Improved voltage margins using linear error-correcting codes in resistor-logic demultiplexers for nanoelectronics," Nanotechnology, vol. 16, pp. 1419-1432, 2005.
    • (2005) Nanotechnology , vol.16 , pp. 1419-1432
    • Kuekes, P.J.1    Robinett, W.2    Williams, R.S.3
  • 12
    • 33646735946 scopus 로고    scopus 로고
    • Defect tolerance in resistor-logic demultiplexers for nanoelectronics
    • P. J. Kuekes, W. Robinett, G. Seroussi, and R. S. Williams, "Defect tolerance in resistor-logic demultiplexers for nanoelectronics," Nanotechnology, vol. 17, pp. 2466-2474, 2006.
    • (2006) Nanotechnology , vol.17 , pp. 2466-2474
    • Kuekes, P.J.1    Robinett, W.2    Seroussi, G.3    Williams, R.S.4
  • 18
    • 0032510985 scopus 로고    scopus 로고
    • A defecttolerant computer architecture: Opportunities for nanotechnology
    • J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defecttolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, p. 1716, 1998.
    • (1998) Science , vol.280 , pp. 1716
    • Heath, J.R.1    Kuekes, P.J.2    Snider, G.S.3    Williams, R.S.4
  • 19
    • 33749029425 scopus 로고    scopus 로고
    • International technology roadmap for semiconductors
    • International Technology Roadmap for Semiconductors, Front-End Process 2004.
    • Front-end Process 2004


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.