Design and optimization of low-voltage low-power Quasi-Floating Gate digital circuits

Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005

Volumn 2005, Issue , 2005, Pages 132-136

  Townsend, Kenneth A ^a   Haslett, James W ^a   Iniewski, Krzysztof ^b  

^a UNIVERSITY OF CALGARY   (Canada)

^b UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; POWER CONSUMPTION; POWER REDUCTION; QUASI-FLOATING GATE;

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; GATES (TRANSISTOR); NATURAL FREQUENCIES; OPTIMIZATION;

DIGITAL CIRCUITS;

EID: 33748907374     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2005.49     Document Type: Conference Paper

References (9)

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