Yield-preferred via insertion based on novel geotopological technology

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 730-735

  Luo, Fangyi ^a   Jia, Yongbo ^b   Dai, Wayne Wei Ming ^a  

^a University of California Santa Cruz   (United States)

^b Nannor Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; FAILURE ANALYSIS; INDUSTRIAL APPLICATIONS; PRODUCT DESIGN;

GEOTOPLOGICAL LAYOUT PLATFORMS; GEOTOPOLOGICAL TECHNOLOGY; INSERTION METHOD; METAL LAYERS;

GEOTECHNICAL ENGINEERING;

EID: 33748614836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118469     Document Type: Conference Paper

References (14)

1. Andrew B. Kahng and Y. C. Pati, "Subwavelength lithography and its potential impact on design and EDA," IEEE/ACM Design Automation Conf, pp. 799-804, 1999.
2. T.C. Huang and C.H. Yao and W.K. Wan and Chin C. Hsia and M.S. Liang, "Numerical modeling and characterization of the stress migration behavior upon various 90 nanometer Cu/Low k interconnects," IEEE International Interconnect Technology Conference, pp. 207-209, 2003.
3. Kelvin Y.Y. Doong and Robin C.J. Wang and S.C. Lin and L.J. Huang and S.Y. Lee and C.C. Chiu and David Su and Kenneth Wu and K.L. Young and Y.K. Peng, "Stress-induced voiding and its geometry dependency characterization, " IEEE International Interconnect Technology Conference, pp. 156-160, 2003.
4. Gang Xu, Li-Da Huang. David Z. Pan and Martin D.F. Wong, "Redundant-via enhanced maze routing for yield improvement," Proc. Asia South Pacific Design Auto. Conf., 2005.
5. TSMC Symposium, 2004.
6. NanoRoute, Cadence Design Systems.
7. SiFix, Sagantec.
8. Wayne Wei-Ming Dai, David Staepelaere, Jeffrey Jue and Tal Dayan, "Cost-driven layout for thin film MCMs," Proc. IEEE MCM Conf, pp. 174-178, 1993.
9. F. Miller Maley, Single-layer wire routing and compaction, MIT Press, Cambridge, MA, 1990.
10. Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai "Interchangeable pin routing with application to package layout," Proc. Intl. Conf. Computeraided Design, Santa Clara, CA, Nov., 1996.
11. S. Zhang and W. Dai, "TEG: a new post-Layout optimization method," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, Num. 2, pp. 1-12, 2003.
12. Hardy Kwok-Shing Leung, "Advanced routing in changing technology landscape," International Symposium on Physical Design, pp. 118-121, 2003.
13. Fangyi Luo, "Layout Wiring Generation," Master's Thesis, University of California, Santa Cruz, 2004.
14. R. M. Warner, Jr., "Applying a composite model to the IC yield problem," IEEE J. Solid-State Circuits, Vol. SC-9, pp. 86-95, 1974.