Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 396-401

  Tabero, Jesús ^a   Septién, Julio ^b   Mecha, Hortensia ^b   Mozos, Daniel ^b  

^a INSTITUTO NACIONAL DE TÉCNICA AEROESPACIAL   (Spain)

^b UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; DELAY CIRCUITS; HEURISTIC PROGRAMMING; TWO DIMENSIONAL;

FRAGMENTATION; HW MANAGEMENT; RECONFIGURABLE SYSTEMS; SEARCH SPACE;

SYSTEMS SCIENCE;

EID: 33748585172     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118397     Document Type: Conference Paper

References (9)

1. K. Compton, S. Hauck, "Reconfigurable computing: a survey of systems and software", ACM Computing Surveys, Vol. 34, No. 2, pp 171-210. June 2002.
2. O. F. Diessel, G. Wigley, "Opportunities for Operating Systems Research in Reconfigurable Computing", Technical Report ACRC-99-018. Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, 1999.
3. O. F. Diessel, H. Elgindy, "On dynamic task scheduling for FPGA-based systems", International Journal of Foundations of Computer Science, IJFCS'01, Vol. 12, No. 5, 2001.
4. K. Bazargan, R. Kastner, M. Sarrafzadeh, "Fast template placement for reconfigurable computing systems", IEEE Design and Test of Computers, Vol. 17, pp 68-83, 2000.
5. H. Walder, C. Steiger, M. Platzner, "Fast online task placement on FPGAs: free space partitioning and 2D-Hashing", IPDPS-2003 (RAW'03), vol. 00, p. 178b, Munich, Germany, April 2003.
6. A. Ahmadinia, C. Bobda, M. Bednara, J. Teich, "A new approach for on-line placement on reconfigurable devices", IPDPS-2004 (RAW'04), vol. 04, no4, p. 134a, 2004.
7. Handa and R. Vemuri, "An efficient algorithm for finding empty space for online FPGA placement," Design Automation Conference, p. 960-965, San Diego, CA, June 2004.
8. J. Tabero J. Septién, H. Mecha, D. Mozos, "A vertex-list approach to 2D HW multitasking management in RTR FPGAs", DCIS 2003, Ciudad Real, Spain, pp. 545-550, Nov 2003.
9. J. Tabero J. Septién, H. Mecha, D. Mozos, "A low fragmentation heuristic for task placement in 2D RTR HW management", FPL 2004, Antwerp, Belgium, pp. 241-250, Sep 2004