Near-memory caching for improved energy consumption

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 105-108

  AbouGhazaleh, Nevine ^a   Childers, Bruce ^a   Mossé, Daniel ^a   Melhem, Rami ^a  

^a University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY MODULE; NEAR-MEMORY CACHING; POWER/ENERGY REDUCTION;

ENERGY CONSERVATION; ENERGY UTILIZATION;

BUFFER STORAGE;

EID: 33748533162     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.79     Document Type: Conference Paper

References (13)

1. D. Elliott, W. Snelgrove and M. Stumm, "Computational RAM: A Memory-SIMD Hybrid and its Application to DSP", in Custom Integrated Circuits Conference, 1992.
2. W. Hsu and J. Smith, "Performance of cached DRAM organizations in vector supercomputers", in Proc. Intl. Symp. on Computer Architecture, pp. 327-336, 1993.
3. A. Hegde, N. Vijaykrishnan, M. Kandemir and M.J. Irwin, "VL-CDRAM: variable line sized cached DRAMs", in Proc. of the Intl. Symp. on Hardware/software codesign & system synthesis, pp. 132-137, 2003.
4. N. AbouGhazaleh, B. Childers, D. Mosse' and R. Melhem, "Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM", in Proc. of the Dagstuhl Seminar on Power-aware Computing Systems, Dagstuhl Research Online Publication Server, April, 03-08 2005.
5. P. Shivakumar and N. Jouppi, "CACTI 3.0: An Integrated Cache Timing, Power, and Area Model", Technical Report 2001.2, Compaq research labs, 2001.
6. "Rambus", 2005, http://www.rambus.com/products.
7. "Simplescalar simulator/PISA Tool Set version 3.0d", http://www.simplescalar.com.
8. "SDRAM and RDRAM modeling for Simplescalar simulator", 2003, http://www.tik.ee.ethz.ch/~ip3/software.
9. A. Lebeck, X. Fan, H. Zeng and C. Ellis, "Power aware page allocation", in Proc. of the Intl. conf. on Architectural support for programming languages and OS, 2000.
10. H. Huang, P. Pillai and K. Shin, "Design and Implementation of Power-Aware Virtual Memory", in USENIX Annual Technical Conf., pp. 57-70, 2003.
11. I. Kadayif, T. Chinoda, M. Kandemir, N. Vijaykirsnan, M. J. Irwin and A. Sivasubramaniam, "vEC: virtual energy counters", in Workshop on Program analysis for software tools and engineering, pp. 28-31, 2001.
12. B. Davis, Moderan DRAM Architectures, PhD thesis, University of Michigan, Ann Arbor, 2000.
13. R. Koganti and G. Kedem, "WCDRAM: A Fully Associative Integrated Cached-DRAM with Wide Cache Lines", Technical report, Duke University, CS dept., 1997.