-
2
-
-
0346778725
-
Leakage power optimization techniques for ultra deep sub-micron multi-level caches
-
N. Kim, D. Blaauw and T. Mudge, "Leakage power optimization techniques for ultra deep sub-micron multi-level caches," Proc. of IEEE/ACM Intl. Conf. CAD, 2003.
-
(2003)
Proc. of IEEE/ACM Intl. Conf. CAD
-
-
Kim, N.1
Blaauw, D.2
Mudge, T.3
-
4
-
-
33748573419
-
An auto-backgate-controlled MT-CMOS circuit
-
H. Makino et al, "An auto-backgate-controlled MT-CMOS circuit," Proc. Symp. VLSI Circuits, 1998.
-
(1998)
Proc. Symp. VLSI Circuits
-
-
Makino, H.1
-
6
-
-
4444254095
-
System level leakage reduction considering interdependence of temperature and leakage
-
L. He, W. Liao and M. Stan, "System level leakage reduction considering interdependence of temperature and leakage," Proc. of IEEE/ACM Design Automation Conf., 2004.
-
(2004)
Proc. of IEEE/ACM Design Automation Conf.
-
-
He, L.1
Liao, W.2
Stan, M.3
-
9
-
-
0042921418
-
Static energy reduction techniques for microprocessor caches
-
June
-
H. Hanson, et al, "Static energy reduction techniques for microprocessor caches," IEEE Tran. On VLSI, vol. 11, no. 3, pp. 303-313, June 2003.
-
(2003)
IEEE Tran. on VLSI
, vol.11
, Issue.3
, pp. 303-313
-
-
Hanson, H.1
-
10
-
-
16244394515
-
Efficient full-chip thermal modeling and analysis
-
Nov.
-
P. Li, L. Pileggi, M, Ashighi and R. Chandra, "Efficient full-chip thermal modeling and analysis," Proc. of IEEE/ACM Intl. Conf. on Computer-Aided Design, Nov. 2004.
-
(2004)
Proc. of IEEE/ACM Intl. Conf. on Computer-aided Design
-
-
Li, P.1
Pileggi, L.2
Ashighi, M.3
Chandra, R.4
-
12
-
-
4444277473
-
Leakage in nano-scale technologies: Mechanisms, impact and design considerations
-
A. Agarwal, C. Kim, S. Mukhopadhyay and K. Roy, "Leakage in nano-scale technologies: mechanisms, impact and design considerations," Proc. of IEEE/ACM DAC, 2004.
-
(2004)
Proc. of IEEE/ACM DAC
-
-
Agarwal, A.1
Kim, C.2
Mukhopadhyay, S.3
Roy, K.4
-
13
-
-
1642310480
-
Circuit and microarchitectural techniques for reducing cache leakage power
-
Feb
-
N. Kim, K. Flautner, D. Blaauw and T. Mudge, "Circuit and microarchitectural techniques for reducing cache leakage power," IEEE Tran. On VLSI, vol. 12, no. 2, Feb 2004.
-
(2004)
IEEE Tran. on VLSI
, vol.12
, Issue.2
-
-
Kim, N.1
Flautner, K.2
Blaauw, D.3
Mudge, T.4
-
16
-
-
0029722759
-
Thermal management of a C4/ceramic-ballgrid array: The Motorola PowerPC 603TM and PowerPC 604TM RISC microprocessors
-
G. Kromann, "Thermal management of a C4/ceramic-ballgrid array: the Motorola PowerPC 603TM and PowerPC 604TM RISC microprocessors," 12th Semiconductor Thermal Measurement and Management Symposium, 1996.
-
(1996)
12th Semiconductor Thermal Measurement and Management Symposium
-
-
Kromann, G.1
-
18
-
-
0033712799
-
New paradigm of predictive MOSFET and interconnect modeling for early circuit design
-
Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," Proc. of IEEE CICC, 2000.
-
(2000)
Proc. of IEEE CICC
-
-
Cao, Y.1
Sato, T.2
Sylvester, D.3
Orshansky, M.4
Hu, C.5
|