An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 52, Issue 8, 2005, Pages 496-500

  Rahman, H ^a   Chakrabarti, C ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

Control point insertion; leakage current reduction; leakage sensitivity (LS); low power design; minimum leakage vector (MLV)

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; LOGIC CIRCUITS; POINT CONTACTS; VECTORS;

CONTROL POINT INSERTION; LEAKAGE CURRENT REDUCTION; LEAKAGE SENSITIVITY (LS); LOW POWER DESIGN; MINIMUM LEAKAGE VECTOR (MLV);

LEAKAGE CURRENTS;

EID: 33748518627     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.849026     Document Type: Article

References (12)

1. S. Borker, “Design challenges of technology scaling,” IEEE Micro, vol. 9, no. 4, pp. 23–29, Jul.-Aug. 1999.
2. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling,” in Proc. Design Automation Conf., Jun. 2003, pp. 169–174.
3. M. Johnson, D. Somasekhar, and K. Roy, “Models and algorithms for bounds on leakage in CMOS circuits,” IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., vol. 18, no. 6, pp. 714–725, Jun. 1999.
4. A. Abdollahi, F. Fallah, and M. Pedram, “Runtime mechanisms for leakage current reduction in CMOS VLSI circuits,” in Proc. ISLPED, Aug. 2002, pp. 213–218.
5. J. Kao, A. Chandrakasan, and D. Antioniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology,” in Proc. Design Automation Conf., 1997, pp. 409–414.
6. L. Wei, Z. Chen, M. Johnson, K. Roy, and V. De, “Design and optimization of low voltage high performance dual threshold CMOS circuits,” in Proc. 35th Design Automation Conf., Jun. 1998, pp. 489–494.
7. S. Narendra, S. Borker, V. De, D. Antoniadis, and A. P. Chandrakasan, “Scaling of stacked effect and its application for leakage reductions,” in Proc. ISLPED, 2001, pp. 195–200.
8. D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, “Analysis and minimization techniques for total leakage considering gate oxide leakage,” in Proc. Design Automation Conf., Jun. 2003, pp. 175–180.
9. S. Mukhopadhyay, C. Neau, R. T. Cakici, A. Agarwal, C. H. Kim, and K. Roy, “Gate leakage reduction for scaled devices using transistor stacking,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 4, pp. 716–730, Aug. 2003.
10. K. Chopra, S. B. K. Vrudhula, and S. Bhardwaj, “Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic,” in Proc. 17th Int. Conf. VLSI Design, Jan. 2004, pp. 240–245.
11. M. Johnson, D. Somasekhar, and K. Roy, “Leakage control with efficient use of transistor stacks in single threshold CMOS,” in Proc. 36th Design Automation Conf., 1999, pp. 442–445.
12. S. Devadas, K. Keutzer, and S. Malik and A. Wang, “Certified timing verification and the transition delay of a logic circuit,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 3, pp. 333–342, Sep. 1994.