Current status and outlook of 3D inspection analysis for semiconductor devices - Efforts towards smart route-cause analysis by new measurement and analysis technology

Hitachi Review

Volumn 55, Issue 2, 2006, Pages 56-60

  Sugimoto, Aritoshi ^a,b,c,d   Kembo, Yukio ^e,f,g   Watanabe, Kenji ^a,f   Yaguchi, Toshie ^a,b,h,i  

^a HITACHI HIGH TECHNOLOGIES CORPORATION   (Japan)

^b JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^c IEEE

^d International Society for Optical Engineering SPIE   (United States)

^e Hitachi Kenki FineTech Co Ltd   (Japan)

^f Japan Society for Precision Engineering (JSPE)   (Japan)

^g Japan Society of Mechanical Engineers JSME   (Japan)

^h Japanese Society of Microscopy (JSM)   (Japan)

ⁱ Microscopy Society of America (MSA)   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL MEASUREMENT METHODS; DEFECT INSPECTION; HITACHI HIGH TECHNOLOGIES CORPORATION (CO); MULTI LAYERED DEVICES;

DEFECTS; ELECTRIC BREAKDOWN; MEASUREMENT THEORY; PROBLEM SOLVING; SHORT CIRCUIT CURRENTS; SURFACE STRUCTURE; THREE DIMENSIONAL;

SEMICONDUCTOR DEVICES;

EID: 33748424837     PISSN: 0018277X     EISSN: 0018277X     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (3)

1. "Extending the Life of Planar CMOS to the Maximum before Focusing on 3D Transistors." NIKKEI MICRODEVICES (Aug. 2005).
2. 2 6T-SRAM Cell and Advanced CMOS Logic Circuits." Symposium on VLSI Technology, p. 106 (June 2005).
3. H. Koyabu et al., "In-line AFM for Semiconductor Process Evaluation," Hitachi Hyoron. pp. 271-274 (Mar. 2002) in Japanese.