����ℰℱect ����olerant layout synthesis

International Journal of Electronics

Volumn 76, Issue 6, 1994, Pages 1121-1133

  Orailoğlu, Alex ^a   Karri, Ramesh ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33748007494     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/00207219408926022     Document Type: Article

References (16)

1. Allan, G. A., Walton, A. J., and Holwill, R. J., 1992, A yield improvement technique for IC layout using local design rules. IEEE Transactions on Computer Aided Design, 11, 1355-1362.
2. Chiluvuri, V., and Koren, I., 1992, New routing and compaction strategies for yield enhancement. Proceedings of the International Workshop on Defect and Fault Tolerance on VLSI Systems, Dallas, Texas, U.S.A., pp. 325-334.
3. Dalal, A. R., Franzon, P. D., and Lorenzetti, M. J., 1993, A layout-driven yield predictor and fault generator for VLSI. IEEE Transactions on Semiconductor Manufacturing, 6, 77-82.
4. de Gyvez, J. P., 1993, Integrated Circuit Defect-Sensitivity: Theory and Computational Models(U.S.A.: Kluwer Academic).
5. Director, S. W., 1992, Optimization of parametric yield. Proceedings of the International Workshop on Defect and Fault Tolerance on VLSI Systems, Dallas, Texas, U.S.A., pp. 1-18.
6. Ferris-Prabhu, A. V., 1989, Defects, faults and semiconductor device yield. Defect and Fault Tolerance in VLSI Systems, Vol. 1, pp. 33-46.
7. Kirkpatrick, S., Gelatt, C. D., and Vecchi, M. P., 1983, Optimization by Simulated annealing. Science, 220(4598), 671-680, May.
8. Koren, I., and Singh, A. D., 1990, Fault tolerance in VLSI circuits. Computer, 23(7), 73-83.
9. Koren, I., and Stapper, C. H., 1989, Yield models for defect tolerant VLSI circuits. A review. Defect and Fault Tolerance in VLSI Systems, Vol. 1 (New York: Plenum), pp. 1-21.
10. Kuh, E. S., and Ohtsuki, T., 1990, Recent advances in VLSI layout. Proceedings of the Institute of Electrical and Electronics Engineers, 78(2), 237-263.
11. LaPaugh, A. S., and Pinter, R. Y., 1990, Channel routing for integrated circuits. Annual Reviews on Computer Science, 307-363.
12. Maly, W., 1990, Computer-aided design for VLSI circuit manufacturability. Proceedings of the Institute of Electrical and Electronics Engineers, 78(2), 356-392.
13. Pitaksanonkul, A., Thanawastien, S., Lursinsap, C., and Gandhi, J. A., 1989, DTR: a defect-tolerant routing algorithm. Proceedings of the 26th Design Automation Conference, Las Vegas, Nevada, U.S.A., pp. 795-798.
14. Stapper, C. H., 1976, LSI yield modeling and process monitoring. IBM Journal of Research and Development, 20, 228-234.
15. Stapper, C. H., Armstrong, F., and Saji, K., 1983, Integrated circuit yield statistics. Proceedings of the Institute of Electrical and Electronics Engineers, 71, 453-470.
16. Yoshimura, T., and Kuh, E. S., 1982, Efficient algorithms for channel routing. IEEE Transactions on Computer Aided Design, 1, 180-190.