Mechanisms of localized charge injection: A technique to characterize gate edge damage in MOS transistors

European Solid-State Device Research Conference

Volumn , Issue , 1997, Pages 560-563

  Sridharan, Anand ^a   Ramgopal Rao, V ^a   Brozek, Tomasz ^b   Werking, James ^c   Viswanathan, Chand R ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b MOTOROLA INC   (United States)

^c SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); PLASMA TURBULENCE;

2-D DEVICE SIMULATIONS; DEEP SUB-MICRON; GATE OXIDE; LOCALIZED CHARGE; OVERLAP REGION; OXIDE THICKNESS; PLASMA EDGES; REVERSE VOLTAGES;

FIELD EFFECT TRANSISTORS;

EID: 33747999908     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.1997.194490     Document Type: Conference Paper

References (4)

1. T. Brozek et al., IEEE ICMTS, March 1997, USA
2. T. Brozek et al., IEDM Tech. Dig., , 1996
3. T.Y. Chan et al., IEDM Tech Dig., 1987
4. ATLAS, SILVACO International, Santa Clara, USA