Silver Metallization for Advanced Interconnects

IEEE Transactions on Advanced Packaging

Volumn 22, Issue 1, 1999, Pages 4-8

  Tuckerman, D B ^a  

^a Georgia Institute of Technology   (United States)

Author keywords

85 85 tests; Corrosion; Electrochemical migration; Low resistivity; Residual stress; Silver dendrites; Silver metallization; Temperature humidity and bias (thb) test

Indexed keywords

EID: 33747937813     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.746536     Document Type: Article

References (8)

1. D. B. Tuckerman and D. Benson"Electrical design techniques fo MCM-D," in Proc. 1EPS Conf., 1994, pp. 69-85.
2. G. DiGiacomoElectrochemistry of Semiconductors and Electronics Englewood, NJ: Noyes, 1992
3. National Technology Roadmap for SemiconductorsSemiconductor Industry Association, 1997.
4. P. A. FlinnA. S. Mack, P. R. Besser, and T. N. Marieb, "Stress induce void formation in metal lines," MRS Bulletin, pp. 26-35, Dec. 1993.
5. CRC Handbook of Chemistry and Physics. Boca RatonEL: CRC 1990.
6. Y. UshikuH. Ono, T. lijima, N. Ninimiya, A. Nishiyama, H. Iwai and H. Hara "Planarized silver interconnect technology with a Ti sel passivation technique for deep sub micron ULSI's," in Proc. IEEE VLS Tech., May 1993, p. 121.
7. T. C. HodgeS. A. Bidstrup-Allen, and P. A. Kohl, "Stresses in thi film metallization," IEEE Trans. Comp., Packag., Manufact. Technol. A vol. 20, pp. 241-250, June 1997.
8. G. DiGiacomoReliability of Electronic Packages and Semiconducto Devices. New York: McGraw-Hill, 1997.