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Volumn , Issue , 1992, Pages 162-169

Efficient fault-tolerant mesh and hypercube architectures

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; FAULT TOLERANCE; MESH GENERATION;

EID: 33747827348     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FTCS.1992.243604     Document Type: Conference Paper
Times cited : (18)

References (20)
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    • S. Dutt and J. P. Hayes, On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures, IEEE Trans. on Computers, val. C-39, no. 4, pp. 490-503, April 1990.
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  • 9
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  • 11
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    • Hayes, J.P.1
  • 13
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  • 14
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    • F. T. Leighton and C. E. Leiserson, Wafer Scale Integration of Systolic Arrays, IEEE Trans. on Computers, val. C-34, no. 5, pp. 448-461, May 1985.
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    • Leighton, F.T.1    Leiserson, C.E.2
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    • The torus: An exercise in constructing a processing surface
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    • A. J. Martin, The Torus: An Exercise in Constructing a Processing Surface, Proc. 2nd Caltech Conf. on VLSI, pp. 527-537, Jan. 1981.
    • (1981) Proc. 2nd Caltech Conf. on VLSI , pp. 527-537
    • Martin, A.J.1
  • 16
    • 84986511249 scopus 로고
    • Minimum k-hamiltonian graphs, II
    • M. Paoli, W. W. Wong and C. K. Wong, Minimum k-Hamiltonian Graphs, II, J. of Graph Theory, Vol. 10, pp. 79-95, 1986.
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  • 17
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    • April
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.