DESIGN OF RM-nc: A RECONFIGURABLE NEUROCOMPUTER FOR MASSIVELY PARALLEL-PIPELINED COMPUTATIONS

Proceedings of the International Joint Conference on Neural Networks

Volumn 2, Issue , 1992, Pages 33-38

  Erdogan, S S ^a   Wahab, Abdul ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; NEURAL NETWORKS; PIPELINE PROCESSING SYSTEMS;

COMMUNICATION AND CONTROL; COMPUTATIONAL ELEMENTS; CONTROL ENVIRONMENT; MASSIVELY PARALLELS; NEURAL NETWORK SIMULATIONS; NEUROCOMPUTERS; PIPELINED COMPUTATION; PROCESSING ELEMENTS; RECONFIGURABLE; RECONFIGURABLE PLATFORMS;

DIGITAL ARITHMETIC;

EID: 33747809991     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.1992.226988     Document Type: Conference Paper

References (13)

1. W B Ligón and U Ramachandran, "Exploring Reconfigurable Architectures", in IEEE, Proc. of the 3rd Symposium on the Frontiers of Massively Parallel Computation, pp. 205-214,1990.
2. R R Shively et al., "A High Performance Reconfigurable Parallel Processing Architecture", in ACM, Proc. of Supercomputing 89, pp. 505-509, 1989.
3. R P Lippmann, "An Introduction to Computing with Neural Nets", IEEE, ASSP Magazine, pp. 4-22, April 1987.
4. R M Kuczewski, M H Myers, W J Crawford, "Neurocomputer Workstations and Processors: Approaches and Applications", in IEEE, Proc. of the first International Conference on Neural Networks, Vol. 3, pp.487-500, June 1987.
5. Akira Iwata et al, "An Artificial Neural Network Accelerator Using General Purpose 24 bits Floating Point Digital Signal Processor", in IEEE, Proc. of the IJCNN, the International Joint Conference on Neural Networks, Vol.2, pp. 171-175, 1989.
6. Takumi Watanabe et al, "Neural Network Simulation on a Massively Parallel Cellular Array Processor: AAP-2", in IEEE, Proc. Ofthe IJCNN, the International Joint Conference on Neural Networks, 1989, Vol.2, pp. 155¬ 161, 1987.
7. E R Kham and N Ling, "Systolic Architectures for Artificial Neural Nets", in Proc. of the IJCNN, The International Joint Conference on Neural Networks, Vol. 1, pp. 620-627, Nov. 1991.
8. C Jutten, A Guerin, J Hérault, "Simulation Machine and Integrated Implementation of Neural Networks: A review of methods problems and realizations", Lecture Notes in Computer Sciences, Neural Networks, Proc. of the 1990 EURASIP Workshop, Springer Verlag, pp. 244-265, 1990.
9. P Messina et al., "Benchmarking advanced Architecture Computers", Concurrency: Practice and Experience, Vol. 2(3), pp. 195-255, September 1990.
10. Dean A Pomerleau et al, "Neural Network Simulation at Warp Speed: How We Got 17 Million Connections Per Second", IEEE, in Proc. of the first International Conference on Neural Networks.
11. M Yasunaga et al, "A Self-learning Neural Net Composed of 1152 Digital Neurons in Wafer-Scale LSIs", in Proc. of the IJCNN, The International Joint Conference on Neural Networks, Vol. 3, pp. 1844-1849, Nov. 1991.
12. S S Erdogan and Abdul Wahab, "Floating Point Sum of Products Evaluation Using Carry-save Representation", submitted to IEEE Trans, on Comp.
13. A Iwata et al, "An artificial Neural Network Accelerator Using General Purpose 24-bit Floating Point Signal Processor", in IEEE, Proc. of the IJCNN, the International Joint Conference on Neural Networks, Vol. 2, pp. 171¬ 175, 1989.