Adaptive phase locked loop for video signal sampling

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1992, Pages 1664-1667

  Bishop, A J ^a   Roberts, G W ^a   Blostein, M L ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ALGORITHMS; CHARGE PUMP CIRCUITS; LOCKS (FASTENERS); OPERATIONAL AMPLIFIERS; PHASE LOCKED LOOPS; SIGNAL PROCESSING; SIGNAL SAMPLING; TRANSCONDUCTANCE;

ACQUISITION TIME; ADAPTIVE PHASE; CHARGE PUMP PLL; CIRCUIT COMPONENTS; LOOP FILTER; SECOND ORDERS; SIGNAL ACQUISITIONS; SYSTEM REQUIREMENTS;

TUNING;

EID: 33747783138     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.1992.230357     Document Type: Conference Paper

References (8)

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3. st Annual Frequency Control Symposium, 1987, pp. 524-526.
4. D. Wulich, M. Bar, The Convergence of a PLL with Variable Parameters, Int. Journal of Circuit Theory and Applications, Vol. 18, 1990, pp. 135-143.
5. F. M. Gardner, Phaselock Techniques, John Wiley & Sons, New York, 1979.
6. K. M. Ware, H-S Lee, and C. G. Sodini, A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors, IEEE JSSC, Vol. 24, No. 6, Dec. 1989.
7. R. C. Den Dulk, Digital PLL Lock-Detection Circuit, Elect. Letters, Vol. 24, No. 14, July, 1988, pp. 880-881.
8. S. H. Khadhouri, S. R. Al-Araji, J. E. Alios, Fast Switching Frequency Synthesizer Employing Adaptive Phase Locked Loop, IEEE Trans. on Consumer Electronics, Vol. CE-31, No. 4, Nov. 1985, pp. 680-686.