A system-integrate ULSI chip containing eleven 4 Mb RAMs, six 64kb SRAMs and an 18k gate array

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 1992-February, Issue , 1992, Pages 52-53

  Sato, Katsuyuki ^a   Fujita, Kenji ^b   Miyazawa, Hideyuki ^a   Shirai, Masayuki ^a   Kobayashi, Mitsuteru ^a   Ishihara, Masamichi ^a   Nakao, Toshiyuki ^b  

^a Device Development Center   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; HEAT RESISTANCE; SILICON WAFERS; ULSI CIRCUITS;

CHIP CONFIGURATION; DIE BONDING; EVALUATION RESULTS; GATE ARRAYS; GRID ARRAYS; SILICON DIE; SYSTEM INTEGRATION; THERMAL SPREADERS;

WSI CIRCUITS;

EID: 33747708646     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1992.200406     Document Type: Conference Paper

References (5)

1. Sawada, K., et al, "A 72k CMOS Channelless Gate Array with Embedded 1Mb Dynamic RAM." IEEE CICC, Proc., pp. 20.3.1-20.3.4, May 1988.
2. Yamashita, K. et al, "A Wafer-Scale 170,000-Gate FET Processor with Built-in Test Circuits," IEEE J. Solid-State Circuits, vol. 23. no. 2, pp. 336-342, Apr. 1988.
3. MacDonald. X., et al., "200Mb Wafer Memory," ISSCC DIGEST OF TECHNICAL PAPERS, pp. 240-241. Feb. 1989.
4. Eaton, S, et al, "A 100ns 64k Dynamic RAM Usizg Redundancy Techniques." ISSCC DIGEST OF TECHNICAL PAPERS, pp. 84-5, Feb. 1981.
5. Shimohigashi, K, et al, "Redundancy Techniques for Dynamic RAMs," Japanese Journal of Applied Physics, vol. 22, Supplement 22-1. pp. 63-67,1983.