A numerical model for simulating MOSFET gate current degradation by considering the interface state generation

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 1996, Pages 115-116

  Yih, C M ^a   Chung, S S ^a   Hsu, C C H ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

INTERFACE STATES;

2-D DEVICE SIMULATIONS; GATE CURRENT; HOT CARRIER STRESS; MEASUREMENT DATA; NEW APPROACHES; STATE GENERATIONS; SUBMICRON DEVICES; SUBSTRATE CURRENT;

MOSFET DEVICES;

EID: 33747504270     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.1996.865301     Document Type: Conference Paper

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