Novel capacitor-less high density low power vertical memory

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 1994, Pages 77-78

  Tiwari, S ^a   Hanafi, H ^a   Hartstein, A ^a   Crabbe E F ^a   Powell, A R ^a   Iyer, S S ^a   Tierney, E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33747234560     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.1994.1009423     Document Type: Conference Paper

References (4)

1. D. J. DiMaria, K. M. DeMeyer, and D. W. Dong, "Dual-electron-injector-structure electrically alterable read-only-memory modeling studies, " IEEE Trans. on El. Dev., ED-28, No. 9, p. 1047 (1981).
2. K. Sunouchi, H. Takato, N. Okabe, T. Yamada, T. Ozaki, S. Inoue, K. Hashimdo, K. Hieda, A. Nitayama, F. Horiguchi, and F. Masuoka, "A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMS." Tech. Dig. of IEDM, p. 23 (1989).
3. T. Hori, T. Ohzone, Y. Odake, and J. Hirase, "A MOSFET with Si-implanted gate-SIO2 insulator for nonvolatile memory applications, " Tech. Dig. of IEDM, p. 473 (1992).
4. H. B. Pein and J. D. Plummer, "Performance of the 3-D sidewall flash EPROM Cell, " Tech. Dig. of IEDM, p. 11 (1993).