Achieving uniform nMOS device power distribution for sub-micron ESD reliability

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 131-134

  Duvvury, C ^a   Diaz, C ^a   Haddock, T ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES;

EMISSION MICROSCOPY; M-TECHNOLOGIES; MULTI FINGERS; NMOS DEVICES; POWER DISTRIBUTIONS; PROTECTION LEVEL; SUB MICRON; SUBMICRON TECHNOLOGIES;

ELECTROSTATIC DEVICES;

EID: 33747060861     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307325     Document Type: Conference Paper

References (13)

1. S. Shabde, G. Simmons, A. Baluni, and R. Back, "Snapback induced gate dielectric breakdown in graded junction nMOS transistors, " IEEE IRPS Symp. Proc., p. 176, 1984.
2. C. Duvvury, R. Rountree, R. McPhee, D. Baglee, A. Hyslop, and L. White, "ESD design considerations for ULSI, " EOS/ESD Symp. Proc., EOS-7, 1985.
3. K. Chen, "The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors, " IEEE Tran. Electron Devices, Vol. 35, No. 12, 1988.
4. C. Duvvury, R. McPhcc, D. Baglcc, and R. Rountrec, "ESD protection reliability in 1 CMOS technologies, " IEEE IRPS Symp. Proa, p. 199, 1986.
5. K. Chen, G. Giles, and D. Scott, "Electrostatic discharge protection for one micron CMOS devices and circuits, " IEEE IEDM Tech. Digest, 1986.
6. K. Krakauer and K. Mistry, "ESD Protection in a 3. 3V sub-micron silicided CMOS technology, " EOS/ESD Symp. Proa, EOS-14, 1992.
7. C. Duwury, R. Rountree, H. Stiegler, T. Polgreen, and D. Corum, " ESD phenomena in graded junction devices, " IEEE IRPS Symp. Proa, p. 71, 1989.
8. S. Daniel and D. Krieger, "Process and design optimization for advanced CMOS I/O ESD Protection Devices, " EOS/ESD Symp. Proa, EOS-12, pp. 206-213, 1990.
9. T. Polgreen and A. Chatcrjcc, "Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow, " EOS/ESD Symp. Proa, EOS-10, 1988.
10. C. Duvvury and C. Diaz, "Dynamic gate coupling of nMOS for efficient output ESD protection, " 1RPS-I992.
11. R. Chapman, ct al., "0. 5 micron CMOS for high performance at 3. 3V, " IEEE IEDM Tech. Digest, 1988.
12. C. Diaz and S. Kang, "New algorithms for circuit simulation of device breakdown, " to be published in IEEE trans, on CAD.
13. N. Khurana, T. Maloney, and W. Yeh, "ESD on CHMOS devices, equivalent circuits, physical models and failure mechanisms, " IEEE IRPS, 1985.