Efficient hardware architectures for modular multiplication on FPGAs

Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 539-542

  Amanor, David Narh ^a   Paar, Christof ^a   Pelzl, Jan ^a   Bunimov, Viktor ^b   Schimmler, Manfred ^b  

^a RUHR UNIVERSITY BOCHUM   (Germany)

^b UNIVERSITY OF KIEL   (Germany)

Author keywords

Cryptography; Efficient implementation; FPGA; Hardware; Modular multiplication; Montgomery multiplication; RSA

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; EFFICIENCY; PUBLIC KEY CRYPTOGRAPHY;

EFFICIENT IMPLEMENTATION; MODULAR MULTIPLICATION; MONTGOMERY MULTIPLICATION; RSA;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746928326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515780     Document Type: Conference Paper

References (5)

1. P. Montgomery, "Modular Multiplication without Trial Division, " Mathematics of Computation, vol. 44, pp. 519-521, 1985.
2. G. Blakley, "A Computer Algorithm for Calculating the Product A · B modulo M," IEEE Transactions on Computers, vol. C-32, no. 5, pp. 497-500, May 1983.
3. V. Bunimov, M. Schimmler, and B. Tolg, "A Complexity-Effective Version of Montgomery's Algorithm," in Workshop on Complexity Effective Designs, ISCA'02, May 2002, http://www.ee.rochester.edu:8080/~albonesi/wced02/.
4. V. Bunimov and M. Schimmler, "Area and Time Efficient Modular Multiplication of Large Integers," in IEEE 14th International Conference on Applicationspecific Systems, Architectures and Processors, June 2003.
5. Y. Kim, W. Kang, and J. Choi, "Implementation of 1024-bit modular processor for RSA cryptosystem," School of Electronic and Electrical Engineering, Kyungpook National University, 1370 Sankyok-Dong, Book-Gu, Taegu, Korea, Tech. Rep., 2000, http://www.ap-asic.org/2000/proceedings/10-4.pdf.