Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4373-4376

  Gupta, Amit Kumar ^a   Nooshabadi, Saeid ^a   Taubman, David ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

BIT PLANE CODER; HARDWARE COST; JPEG 2000; JPEG2000 IMAGE COMPRESSION STANDARD; LARGE SPAN; LOWER LIMITS; MEMORY ACCESS; MEMORY ARCHITECTURE; MEMORY CONTROLLER; MEMORY REQUIREMENTS;

CONSUMER PRODUCTS; IMAGE COMPRESSION; SEMICONDUCTOR QUANTUM DOTS;

DIGITAL IMAGE STORAGE;

EID: 33746924733     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465600     Document Type: Conference Paper

References (9)

1. JPEG 2000 Part I Final Committee Draft Version 1.0, ISO/IEC JTC1/SC29/WG1 N1646R, Mar. 2000.
2. D. Taubman, "High Performance scalable image compression with EBCOT", IEEE Trans. Image Processing, vol. 9, pp. 1158-1170, July 2000.
3. D. S. Taubman and M. W. Marcellin, JPEG 2000: Image Compression, Fundamentals, Standards and Practice. Norwell, MA:Kluwer, 2002.
4. Chung-Jr Lian, Kuan-Fu Chen, Hong-Hui Chen, Liang-Gee Chen, "Analysis and architecture design of block-coding engine for EBCOT in JPEG2000", in IEEE Tran. Circuits and Systems for Video Technology, vol. 13, pp. 219-230, March 2003.
5. Amit Kr. Gupta, D. Taubman, S. Nooshabadi, "High speed parallel pipeline architecture for Bit-Plane Coder of JPEG2000 encoder", accepted in IEEE MWSCAS, 2004.
6. Hung-Chi Fang, Tu-Chih Wang, Chung-Jr Lian, Te-Hao Chang and Liang-Gee Chan, "High speed memory efficient EBCOT architecture for JPEG2000", in Proc. IEEE Int. Symp.Circuits and Systems (ISCAS'03), vol. 2, pp. 25-28, May 2003.
7. Kishore Andra, Tinku Acharya, Chaitali Chakrabarti, "Efficient VLSI implementation of Bit Plane Coder of JPEG2000", in Proc. SPIE Int. Conf. Applications of Digital Image Processing XXIV, vol. 4472, pp. 246-257.
8. STMicroelectronics product specification documents DPHS9, MPA9gp, and SPSMALL9gp.
9. J. H. Mulder, N. T. Quach, and M. J. Flynn, "An area model for on-chip memories and its application", IEEE Trans. Solid-State Circults, vol. 26, pp. 98-106, Feb. 1991.