FPGA interconnect fault tolerance

Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 725-726

  Campregher, Nicola ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33746912750     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515827     Document Type: Conference Paper

References (3)

1. P. Simon, "Yield modeling for deep sub-micron IC design," PhD Thesis, University of Eindhoven, 2001.
2. N. Campregher, P. Cheung, G. Constantinides, and M. Vasilko, "Analysis of yield loss due to random photolithographic defects in the interconnect structure of fpgas," in Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, 2005.
3. N. Campregher, P. Y. K. Cheung, and M. Vasilko, BIST Based Interconnect Fault Location for FPGAs, 3203rd ed., ser. Lecture Notes in Computer Science, 2004.