A brunch from the coffee table-case study in noc platform design

Interconnect-Centric Design for Advanced SoC and NoC

Volumn , Issue , 2005, Pages 425-453

  Ahonen, Tapani ^a   Virtanen, Seppo ^b   Kylliäainen, Juha ^a   Truscan, Dragos ^c   Kasanko, Tuukka ^a   Sigüuenza Tortosa, David ^a   Ristimäaki, Tapio ^a   Paakkulainen, Jani ^a   Nurmi, Tero ^b   Saastamoinen, Ilkka ^a   Isäannäainen, Hannu ^a   Lilius, Johan ^c   Nurmi, Jari ^a   Isoaho, Jouni ^b  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b UNIVERSITY OF TURKU   (Finland)

^c ÅBO AKADEMI UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33746885046     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/1-4020-7836-6_16     Document Type: Chapter

References (21)

1. T. Ahonen, T. Nurmi, J. Nurmi, and J. Isoaho. Block-wise extraction of rent's exponents for an extensible processor. In IEEE Computer Society Annual Symposium on VLSI, pages 193-199, Tampa, Florida, February 2003.
2. D. I. August, K. Keutzer, S. Malik, and A. R. Newton. A disciplined approach to the development of platform architectures. Microelectronics Journal, 33(11), November 2002.
3. H. Corporaal. Microprocessor Architectures-from VLIW to TTA. John Wiley and Sons Ltd., Chichester, West Sussex, England, 1998.
4. S. Deering and R. Hinden. Internet protocol, version 6 (IPv6) specification. RFC 2460, December 1998.
5. M. Keating and P. Bricaud. Reuse Methodology Manual for System-on-a-Chip Designs. Kluwer Academic Publishers, Boston, second edition, June 1999. 312 pp.
6. J. Kylliäinen, J. Nurmi, and M. Kuulusa. COFFEE-A Core for Free. In Proceedings of the International Symposium on System-on-Chip, Tampere, Finland, November 2003.
7. B. S. Landman and R. L. Russo. On a pin versus block relationship for partitions of logic graphs. IEEE Transactions on Computers, C20(12):1469-1479, December 1971.
8. J. Lilius and D. Truscan. UML-driven TTA-based protocol processor design. In Proceedings of the 2002 Forum for Design and Specification Languages (FDL'02), Marseille, France, September 2002.
9. J. Lilius, D. Truscan, and S. Virtanen. Fast Evaluation of Protocol Processing Architectures for IPv6 Routing. In Proceedings of the 2003 Design, Automation and Test in Europe conference (DATE'03), Munich, Gemany, March 2003.
10. J. Muttersbach, T. Villiger, and W. Fichtner. Practical design of globally-asynchronous locally-synchronous systems. In Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eilat, Israel, April 2000.
11. J. Muttersbach, T. Villiger, H. Kaeslin, N. Felber, and W. Ficht-ner. Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems. In Proceedings of the 12th Annual IEEE International ASIC/SOC Conference, Washington DC, USA, September 1999.
12. OCP-IP Association. Open Core Protocol Specification Release 1.0. OCP-IP, 2001. www.ocpip.org.
13. T. Ristim̈aki and J. Nurmi. Implementation of a fast 1024-bit RSA encryption on platform FPGA. In Proceedings of the 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems, Poznan, Poland, April 2003.
14. R. L. Rivest, A. Shamir, and L. Adleman. A method of obtaining digital signatures and public-key cryptosystems. Communications of the ACM, 21(2):120-126, 1978.
15. I. Saastamoinen, D. Sigüenza-Tortosa, and J. Nurmi. An IP-based on-chip packet-switched network. In A. Jantsch and H. Tenhunen, editors, Networks on chip, chapter 10, pages 193-213. Kluwer Academic, 2003.
16. D. Tabak and G. J. Lipovski. MOVE architecture in digital controllers. IEEE Transactions on Computers, 29(2):180-190, February 1980.
17. S. Virtanen and J. Lilius. The TACO protocol processor simulation environment. In Proceedings of the 9th International Symposium on Hardware/Software Codesign (CODES'01), pages 201-206, Copenhagen, Denmark, April 2001.
18. S. Virtanen, J. Lilius, T. Nurmi, and T. Westerlund. TACO: Rapid design space exploration for protocol processors. In the Ninth IEEE/DATC Electronic Design Processes Workshop Notes, Monterey, CA, USA, April 2002.
19. S. Virtanen, J. Lilius, and T. Westerlund. A processor architecture for the TACO protocol processor development framework. In Proceedings of the 18th IEEE NORCHIP Conference, pages 204-211, Tu rku, Finland, November 2000.
20. S. Virtanen, D. Truscan, and J. Lilius. TACO IPv6 router-a case study in protocol processor design. Technical Report 528, Turku Centre for Computer Science, Turku, Finland, April 2003.
21. TM, April 2001. www.vsi.org.