Using complete-1-distinguishability for FSM equivalence checking

ACM Transactions on Design Automation of Electronic Systems

Volumn 6, Issue 4, 2001, Pages 569-590

  Ashar, Pranav ^a,c   Gupta, Aarti ^a,c   Malik, Sharad ^b,d  

^a NEC Corporation of America   (United States)

^b PRINCETON UNIVERSITY   (United States)

^c NEC LABORATORIES AMERICA   (United States)

^d Princeton University   (United States)

Author keywords

Algorithms; Bisimulation relation; Complete 1 distinguishability; Equivalence checking; Finite state machine equivalence; Sequential logic synthesis; Theory; Verification

Indexed keywords

EID: 33746838930     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/502175.502183     Document Type: Article

References (23)

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