Efficient equivalence checking of multi-phase designs using phase abstraction and retiming

ACM Transactions on Design Automation of Electronic Systems

Volumn 3, Issue 4, 1998, Pages 600-625

  Hasteer, G ^a   Mathur, A ^a   Bannerjee, P ^b  

^a Ambit Design Systems   (United States)

^b NORTHWESTERN UNIVERSITY   (United States)

Author keywords

Binary decision diagram; Encoding density; Multi phase FSM; Product machine; Sequential hardware equivalence; Steady states

Indexed keywords

EID: 33746770401     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/296333.296348     Document Type: Article

References (15)

1. BRAYTON, R., ET AL. 1995. VIS: A system for verification and synthesis. Tech. Rep. Electronics Research Lab. Univ. California-Berkeley, Berkeley, CA.
2. CABODI, G., CAMURATI, P., LAVAGNO, L., AND QUER, S. 1997. Verification and synthesis of counters based on symbolic techniques. In Proceedings of the European Design Automation Conference (Mar.). 176-181.
3. CHENG, S., RANJAN, R., AND BRAYTON, R. 1996. Modeling multi-phase systems and level-sensitive latches in VIS. VIS User Documentation - http://www-cad.eecs.berkeley.edu/~-vis/ doc/two_phase.html (Dec.).
4. COUDERT, O., AND MADRE, J. 1990. A unified framework for formal verification of sequential circuits. In Proceedings of the International Conference on Computer-Aided Design, (Nov.).
5. HASTEER, G., MATHUR, A., AND BANERJEE, P. 1997. A framework for equivalence checking of multi-phase FSMS. In Proceedings of High-Level Design Validation and Test Symposium, (Oakland, CA, Nov.).
6. HASTEER, G., MATHUR, A., AND BANERJEE, P. 1998. An implicit algorithm for finding steady states and its application to FSM verification. In Proceedings of the 35th Design Automation Conference, (San Francisco, CA, June).
7. LEISERSON, C., AND SAXE, J. 1991. Retiming synchronous circuitry. Algorithmica 6, 5-35.
8. MAHESHWARI, N., AND SAPATNEKAR, S. 1997. An improved algorithm for minimum-area retiming. In Proceedings of the 34th Design Automation Conference. (Anaheim, CA, May). 2-7.
9. PIXLEY, C. 1992. A theory an implementation of sequential hardware equivalence. IEEE Trans. Computer-Aided Des. (Dec.). 1469-1494.
10. RANJAN, R., Aziz, A., PLESSIER, C., PIXLEY, C., AND BRAYTON, R. 1995. Efficient BDD algorithms for FSM synthesis and verification. In Proceedings of the International Workshop on Logic Synthesis (Lake Tahoe, NV, May).
11. SHENOY, N., AND RUDELL, R. 1994. Efficient implementation of retiming. In Proceedings of the International Conference on Computer-Aided Design (San Jose, CA, Nov.).
12. SINGHAL, V. 1996. Design replacements for safe replacability. Ph.D. dissertation. Univ. California, Berkeley.
13. SINGHAL, V., PIXLEY, C., RUDELL, R., AND BRAYTON, R. 1995. The validity of retiming sequential circuits. In Proceedings of the Design Automation Conference (June).
14. TOUATI, H., AND BRAYTON, R. 1993. Computing the initial states of retimed circuits. IEEE Trans. Computer-Aided Des., (Jan.), 157-162.
15. TOUATI, H., SAVOJ, H., LIN, B., BRAYTON, R., AND SANGIOVANNI-VINCENTELLI, A. 1990, Implicit state enumeration of finite state machines using BDDs. In Proceedings of the International Conference on Computer-Aided Design (Nov.).