DAGGER: A novel generic methodology for FPGA bitstream generation and its software tool implementation

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Siozios, K ^a   Koutroumpezis, G ^a   Tatas, K ^a   Soudris, D ^a   Thanailakis, A ^a  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

Author keywords

Bitstream generator; FPGA; Partial; Reconfiguration; Run time; Tool development

Indexed keywords

BITSTREAM GENERATOR; PARTIAL; RECONFIGURATION; RUN-TIME; TOOL DEVELOPMENT;

ALGORITHMS; COMPUTER AIDED SOFTWARE ENGINEERING; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS; GRAPHICAL USER INTERFACES; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

DISTRIBUTED COMPUTER SYSTEMS;

EID: 33746277585     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.158     Document Type: Conference Paper

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