An automated fine-grain pipelining using domino style asynchronous library

Proceedings - International Conference on Application of Concurrency to System Design, ACSD

Volumn 2005, Issue , 2005, Pages 68-76

  Smirnov, Alexander ^a   Taubin, Alexander ^a   Su, Ming ^a   Karpovsky, Mark ^a  

^a Department of Electrical and Computer Engineering ^*  (United States)

Author keywords

ASIC; Asynchronous EDA; HDL; QDI; Synthesis

Indexed keywords

ASYNCHRONOUS EDA; HDL; QUASI-DELAY-INSENSITIVE (QDI); REGISTER TRANSFER LEVEL (RTL);

COMPUTER AIDED ANALYSIS; FREQUENCY CONVERTERS; INFORMATION SERVICES; INTEGRATED CIRCUIT LAYOUT; LARGE SCALE SYSTEMS;

VLSI CIRCUITS;

EID: 33746238162     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSD.2005.3     Document Type: Conference Paper

References (26)

1. Ligthart, M., et al., Asynchronous Design Using Commercial HDL Synthesis Tools, in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2000, IEEE Computer Society Press, p. 114-125.
2. Linder, D.H. and J.C. Harden, Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry. IEEE Transactions on Computers, 1996.45(9): p. 1031-1044.
3. Blunno, I., et al. Handshake protocols for desynchronization, in International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2004.
4. Kondratyev, A. and K. Lwin, Design of Asynchronous Circuits using Synchronous CAD Tools. IEEE Design & Test of Computers, 2002. 19(4): p. 107-117.
5. Cortadella, J., et al. Coping with the variability of combinational logic delays, in Int. Conf. on Computer Design (ICCD). 2004. San Jose.
6. Reese, R.B., M.A. Thornton, and C. Traver. A Fine-Grain Phased Logic CPU. in IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003). 2003. Tampa, Florida.
7. Hrishikesh, M.S., et al. The Optimal Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays, in 29th Int'l Symp. Computer Architecture. 2002: IEEE CS Press.
8. Hartstein, A. and T.R. Puzak. Optimum Power/Performance Pipeline Depth, in MICRO-36 International Symposium on Microarchitecture. 2003.
9. Singh, M. and S.M. Nowick, MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines, in Proc. International Conf. Computer Design (ICCD). 2001. p. 9-17.
10. Sutherland, I. and S. Fairbanks, GasP: A Minimal FIFO Control, in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2001, IEEE Computer Society Press, p. 46-53.
11. Schuster, S., et al. Asynchronous Interlocked Pipelined CMOS Circuits Operating at 3.3-4.5 GHz. in International Solid-State Circuits Conference. 2000.
12. Singh, M. and S.M. Nowick, Fine-grain pipelined asynchronous adders for high-speed DSP applications, in Proceedings of the IEEE Computer Society Workshop on VLSI. 2000, IEEE Computer Society Press, p. 111-118.
13. Singh, M. and S.M. Nowick, High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths, in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2000, IEEE Computer Society Press, p. 198-209.
14. Ferretti, M. and P.A. Beerel, Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding, in Proc. Design, Automation and Test in Europe (DATE). 2002. p. 1008-1015.
15. Choy, C.-s., et al. A fine-grain asynchronous pipeline reaching the synchronous speed, in ASIC. 2001. Shanghai, China.
16. Nowick, M.S.a.S.M, High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. Proceedings of the 6th IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems ("Async-2000"), Eilat, Israel, 2000.
17. Ozdag, R.O. and P.A. Beerel, High-Speed QDI Asynchronous Pipelines, in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2002. p. 13-22.
18. Fulcrum Microsystems Inc. Web site: http://www.fulcrummicro.com/technology.htm.
19. Ozdag, R.O. and P.A. Beerel. A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implementated with QDI Templates, in International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2004.
20. Weaver: GTL synthesis flow. http://async.bu.edu/weaver/. 2004.
21. Renaudin, M., P. Vivet, and F. Robin, A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to HDL Translation, in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. 1999. p. 135-144.
22. Blunno, I. and L. Lavagno, Automated synthesis of micro-pipelines from behavioral Verilog HDL, in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2000. IEEE Computer Society Press, p. 84-92.
23. Smirnov, A., et al. Gate Transfer Level Synthesis as an Automated Approach to Fine-Grain Pipelining, in Workshop on Token Based Computing (ToBaCo). 2004. Bologna, Italy.
24. Kim, S. and P.A. Beerel, Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm, in Proc. International Conf. Computer-Aided Design (ICCAD). 2000.
25. Yang, S., Logic Synthesis and Optimization Benchmarks Version 3.0.1991, Microelectronics center of North Carolina.
26. Verbauwhede, I., P. Schaumont, and H. Kuo, Design and Performance Testing of a 2.29-GB/s Rijndael Processor. IEEE Journal of Solid-State Circuits, 2003. 38(3): p. 569-572.