A methodology to investigate UWB digital receiver sensitivity to clock jitter

2003 IEEE Conference on Ultra Wideband Systems and Technologies, UWBST 2003 - Conference Proceedings

Volumn , Issue , 2003, Pages 126-130

  Pelissier, M ^a,b   Denis, B ^b   Morche, D ^b  

^a CEA GRENOBLE   (France)

^b Service Systhes Pour i'Lnformation et les TMcommunications DCpmement Systemes Pour i'Lnformation et la SmtC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

RADIO RECEIVERS; TIMING JITTER;

ANALYTICAL EXPRESSIONS; CLOCK SYNTHESIZER; DELAY-LOCKED LOOPS; DIGITAL RECEIVERS; JITTER PERFORMANCE; PHASE LOCKED LOOP (PLL); SAMPLING PROCESS; VERY HIGH FREQUENCY;

CLOCKS;

EID: 33746027404     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/UWBST.2003.1267816     Document Type: Conference Paper

References (9)

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