Dynamic specialisation of XC6200 FPGAs by partial evaluation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1482, Issue , 1998, Pages 298-307

  McKay, Nicholas ^a   Singh, Satnam ^b  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

DYNAMIC RE-CONFIGURATION; FPGA CIRCUITS; PARTIAL EVALUATION; RUNTIMES; SPECIALISATION;

COMPUTER CIRCUITS;

EID: 33745982287     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0055257     Document Type: Conference Paper

References (10)

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2. H.T. Kung. Why Systolic Architectures. IEEE Computer. January 1982.
3. National Bureau of Standards. Data Encryption Standard (DES), Technical Report, National Bureau of Standards (USA), Federal Information Processing Standards, Publication 46, National Technical Information Services, Springfield, Virginia, April 1997.
4. N.D. Jones, C.K. Gomard, and P. Sestoft, Partial Evaluation and Automatic Program Generation, Prentice-Hall, 1993.
5. Jason Leonard and William H. Mangione-Smith. A Case Study of Partially Evaluated Hardware Circuits: Key-Specific DES. FPL97. 1997.
6. M. Sheeran, G. Jones. Circuit Design in Ruby. Formal Methods for VLSI Design, J. Stanstrup, North Holland, 1992.
7. Satnam Singh and Pierre Bellec. Virtual Hardware for Graphics Applications using FPGAs. FCCM'94. IEEE Computer Society, 1994.
8. Satnam Singh. Architectural Descriptions for FPGA Circuits. FCCM'95. IEEE Computer Society. 1995.
9. Michael J. Wirthlin and Brad L. Hutchings. Improving Functional Density Through Run-Time Constant Propagation. FPGA'97. 1997.
10. Xilinx. XC6200 FPGA Family Data Sheet. Xilinx Inc. 1995.