Advanced surface cleaning strategy for 65nm CMOS device performance enhancement

Solid State Phenomena

Volumn 103-104, Issue , 2005, Pages 37-40

  Arnaud, F ^a   Bernard, H ^a   Beverina, A ^a   El Farhane, R ^b   Duriez, B ^b   Barla, K ^a   Levy, D ^a  

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

CMOS device performance; Dopant consumption; Low temperature cleaning

Indexed keywords

CMOS INTEGRATED CIRCUITS; TEMPERATURE;

65NM CMOS; CLEANING STRATEGIES; CMOS DEVICES; GATE ETCH; LOW TEMPERATURES; SILICON CONSUMPTION; SILICON RECESS; TRANSISTOR PERFORMANCE;

SURFACE CLEANING;

EID: 33745956584     PISSN: 10120394     EISSN: 16629779     Source Type: Book Series    
DOI: 10.4028/www.scientific.net/SSP.103-104.37     Document Type: Conference Paper

References (4)

1. T. Fukai et al, VLSI symposium (2003) p.83-84
2. Y.H. Lee et al, IEDM tech.digest (2003) p.353-354
3. J.P Carrere et al, ESSDERC proc (2003) p.235
4. S. Petitdidier et al, UCPSS proc (2002) p.187-190