Strategic use of SEE mitigation techniques for the development of the ESA microprocessors: Past, present, and future

Proceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005

Volumn 2005, Issue , 2005, Pages 319-323

  Pouponnot, André L R ^a  

^a EUROPEAN SPACE AGENCY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; IONIZATION; RADIATION EFFECTS; SPACE APPLICATIONS; SPACE RESEARCH;

DESIGN CONSTRAINTS; EUROPEAN SPACE AGENCY (ESA); GEOMETRY SHRINKING; SINGLE EVENT EFFECTS (SEE);

MICROPROCESSOR CHIPS;

EID: 33745482397     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.66     Document Type: Conference Paper

References (5)

1. www.dynexsemi.com/products/sos/microprocessors.htm
2. th IEEE Int. Symp. Fault-Tolerant Computing (FTCS-24), Austin, USA, pp. 128-130, June 1994.
3. www.estec.esa.nl/wsmwww/erc32
4. www.gaisler.com/products/processor.html
5. J. Gaisler, "A Portable and Fault-Tolerant Microprocessor based on the SPARC V8 Architecture," Proc. IEEE/IFIP Int. Conf. on Dependable Systems and Networks (DSN-2002), Washington, DC, USA, pp. 409-415, 2002.