Automatically partitioning packet processing applications for pipelined architectures

ACM SIGPLAN Notices

Volumn 40, Issue 6, 2005, Pages 237-248

  Dai, Jinquan ^a   Huang, Bo ^a   Li, Long ^a   Harrison, Luddy ^b  

^a INTEL CORPORATION   (China)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Live Set Transmission; Network Processor; Packet Processing; Parallel; Pipelining Transformation; Program Partition

Indexed keywords

LIVE-SET TRANSMISSION; NETWORK PROCESSOR; PACKET PROCESSING; PARALLEL PROCESSING ENGINES (PE); PIPELINING TRANSFORMATION; PROGRAM PARTITION;

BENCHMARKING; C (PROGRAMMING LANGUAGE); COMPUTER PROGRAMMING; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; PROGRAM PROCESSORS;

PACKET NETWORKS;

EID: 33745248654     PISSN: 03621340     EISSN: 03621340     Source Type: Journal    
DOI: 10.1145/1064978.1065039     Document Type: Article

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