Instruction-level test methodology for CPU core self-testing

ACM Transactions on Design Automation of Electronic Systems

Volumn 10, Issue 4, 2005, Pages 673-689

  Shamshiri, Saeed ^a   Esmaeilzadeh, Hadi ^a   Navabi, Zainalabdein ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

BIST; CPU core testing; Instruction level testing; Pipelined processor; Software based self testing; Test instruction set

Indexed keywords

EID: 33745183746     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1109118.1109124     Document Type: Conference Paper

References (16)

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